Lines Matching +full:emc +full:- +full:timings +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
31 #define EMC_FBIO_CFG5 0x104
32 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
33 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
36 #define EMC_INTSTATUS 0x0
39 #define EMC_CFG 0xc
44 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
47 #define EMC_REFCTRL 0x20
48 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
51 #define EMC_TIMING_CONTROL 0x28
52 #define EMC_RC 0x2c
53 #define EMC_RFC 0x30
54 #define EMC_RAS 0x34
55 #define EMC_RP 0x38
56 #define EMC_R2W 0x3c
57 #define EMC_W2R 0x40
58 #define EMC_R2P 0x44
59 #define EMC_W2P 0x48
60 #define EMC_RD_RCD 0x4c
61 #define EMC_WR_RCD 0x50
62 #define EMC_RRD 0x54
63 #define EMC_REXT 0x58
64 #define EMC_WDV 0x5c
65 #define EMC_QUSE 0x60
66 #define EMC_QRST 0x64
67 #define EMC_QSAFE 0x68
68 #define EMC_RDV 0x6c
69 #define EMC_REFRESH 0x70
70 #define EMC_BURST_REFRESH_NUM 0x74
71 #define EMC_PDEX2WR 0x78
72 #define EMC_PDEX2RD 0x7c
73 #define EMC_PCHG2PDEN 0x80
74 #define EMC_ACT2PDEN 0x84
75 #define EMC_AR2PDEN 0x88
76 #define EMC_RW2PDEN 0x8c
77 #define EMC_TXSR 0x90
78 #define EMC_TCKE 0x94
79 #define EMC_TFAW 0x98
80 #define EMC_TRPAB 0x9c
81 #define EMC_TCLKSTABLE 0xa0
82 #define EMC_TCLKSTOP 0xa4
83 #define EMC_TREFBW 0xa8
84 #define EMC_ODT_WRITE 0xb0
85 #define EMC_ODT_READ 0xb4
86 #define EMC_WEXT 0xb8
87 #define EMC_CTT 0xbc
88 #define EMC_RFC_SLR 0xc0
89 #define EMC_MRS_WAIT_CNT2 0xc4
91 #define EMC_MRS_WAIT_CNT 0xc8
92 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
94 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
97 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
99 #define EMC_MRS 0xcc
102 #define EMC_EMRS 0xd0
103 #define EMC_REF 0xd4
104 #define EMC_PRE 0xd8
106 #define EMC_SELF_REF 0xe0
107 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
110 #define EMC_MRW 0xe8
112 #define EMC_MRR 0xec
114 #define LPDDR2_MR4_TEMP_SHIFT 0
116 #define EMC_XM2DQSPADCTRL3 0xf8
117 #define EMC_FBIO_SPARE 0x100
119 #define EMC_FBIO_CFG6 0x114
120 #define EMC_EMRS2 0x12c
121 #define EMC_MRW2 0x134
122 #define EMC_MRW4 0x13c
123 #define EMC_EINPUT 0x14c
124 #define EMC_EINPUT_DURATION 0x150
125 #define EMC_PUTERM_EXTRA 0x154
126 #define EMC_TCKESR 0x158
127 #define EMC_TPD 0x15c
129 #define EMC_AUTO_CAL_CONFIG 0x2a4
131 #define EMC_AUTO_CAL_INTERVAL 0x2a8
132 #define EMC_AUTO_CAL_STATUS 0x2ac
134 #define EMC_STATUS 0x2b4
137 #define EMC_CFG_2 0x2b8
138 #define EMC_CFG_2_MODE_SHIFT 0
141 #define EMC_CFG_DIG_DLL 0x2bc
142 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
143 #define EMC_RDV_MASK 0x2cc
144 #define EMC_WDV_MASK 0x2d0
145 #define EMC_CTT_DURATION 0x2d8
146 #define EMC_CTT_TERM_CTRL 0x2dc
147 #define EMC_ZCAL_INTERVAL 0x2e0
148 #define EMC_ZCAL_WAIT_CNT 0x2e4
150 #define EMC_ZQ_CAL 0x2ec
151 #define EMC_ZQ_CAL_CMD BIT(0)
158 #define EMC_XM2CMDPADCTRL 0x2f0
159 #define EMC_XM2DQSPADCTRL 0x2f8
160 #define EMC_XM2DQSPADCTRL2 0x2fc
161 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
163 #define EMC_XM2DQPADCTRL 0x300
164 #define EMC_XM2DQPADCTRL2 0x304
165 #define EMC_XM2CLKPADCTRL 0x308
166 #define EMC_XM2COMPPADCTRL 0x30c
167 #define EMC_XM2VTTGENPADCTRL 0x310
168 #define EMC_XM2VTTGENPADCTRL2 0x314
169 #define EMC_XM2VTTGENPADCTRL3 0x318
170 #define EMC_XM2DQSPADCTRL4 0x320
171 #define EMC_DLL_XFORM_DQS0 0x328
172 #define EMC_DLL_XFORM_DQS1 0x32c
173 #define EMC_DLL_XFORM_DQS2 0x330
174 #define EMC_DLL_XFORM_DQS3 0x334
175 #define EMC_DLL_XFORM_DQS4 0x338
176 #define EMC_DLL_XFORM_DQS5 0x33c
177 #define EMC_DLL_XFORM_DQS6 0x340
178 #define EMC_DLL_XFORM_DQS7 0x344
179 #define EMC_DLL_XFORM_QUSE0 0x348
180 #define EMC_DLL_XFORM_QUSE1 0x34c
181 #define EMC_DLL_XFORM_QUSE2 0x350
182 #define EMC_DLL_XFORM_QUSE3 0x354
183 #define EMC_DLL_XFORM_QUSE4 0x358
184 #define EMC_DLL_XFORM_QUSE5 0x35c
185 #define EMC_DLL_XFORM_QUSE6 0x360
186 #define EMC_DLL_XFORM_QUSE7 0x364
187 #define EMC_DLL_XFORM_DQ0 0x368
188 #define EMC_DLL_XFORM_DQ1 0x36c
189 #define EMC_DLL_XFORM_DQ2 0x370
190 #define EMC_DLL_XFORM_DQ3 0x374
191 #define EMC_DLI_TRIM_TXDQS0 0x3a8
192 #define EMC_DLI_TRIM_TXDQS1 0x3ac
193 #define EMC_DLI_TRIM_TXDQS2 0x3b0
194 #define EMC_DLI_TRIM_TXDQS3 0x3b4
195 #define EMC_DLI_TRIM_TXDQS4 0x3b8
196 #define EMC_DLI_TRIM_TXDQS5 0x3bc
197 #define EMC_DLI_TRIM_TXDQS6 0x3c0
198 #define EMC_DLI_TRIM_TXDQS7 0x3c4
199 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
200 #define EMC_SEL_DPD_CTRL 0x3d8
207 ((0xf << 2) | BIT(8))
209 ((0x3 << 2) | BIT(5) | BIT(8))
210 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
211 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
212 #define EMC_TXSRDLL 0x3e4
213 #define EMC_CCFIFO_ADDR 0x3e8
214 #define EMC_CCFIFO_DATA 0x3ec
215 #define EMC_CCFIFO_STATUS 0x3f0
216 #define EMC_CDB_CNTL_1 0x3f4
217 #define EMC_CDB_CNTL_2 0x3f8
218 #define EMC_XM2CLKPADCTRL2 0x3fc
219 #define EMC_AUTO_CAL_CONFIG2 0x458
220 #define EMC_AUTO_CAL_CONFIG3 0x45c
221 #define EMC_IBDLY 0x468
222 #define EMC_DLL_XFORM_ADDR0 0x46c
223 #define EMC_DLL_XFORM_ADDR1 0x470
224 #define EMC_DLL_XFORM_ADDR2 0x474
225 #define EMC_DSR_VTTGEN_DRV 0x47c
226 #define EMC_TXDSRVTTGEN 0x480
227 #define EMC_XM2CMDPADCTRL4 0x484
228 #define EMC_XM2CMDPADCTRL5 0x488
229 #define EMC_DLL_XFORM_DQS8 0x4a0
230 #define EMC_DLL_XFORM_DQS9 0x4a4
231 #define EMC_DLL_XFORM_DQS10 0x4a8
232 #define EMC_DLL_XFORM_DQS11 0x4ac
233 #define EMC_DLL_XFORM_DQS12 0x4b0
234 #define EMC_DLL_XFORM_DQS13 0x4b4
235 #define EMC_DLL_XFORM_DQS14 0x4b8
236 #define EMC_DLL_XFORM_DQS15 0x4bc
237 #define EMC_DLL_XFORM_QUSE8 0x4c0
238 #define EMC_DLL_XFORM_QUSE9 0x4c4
239 #define EMC_DLL_XFORM_QUSE10 0x4c8
240 #define EMC_DLL_XFORM_QUSE11 0x4cc
241 #define EMC_DLL_XFORM_QUSE12 0x4d0
242 #define EMC_DLL_XFORM_QUSE13 0x4d4
243 #define EMC_DLL_XFORM_QUSE14 0x4d8
244 #define EMC_DLL_XFORM_QUSE15 0x4dc
245 #define EMC_DLL_XFORM_DQ4 0x4e0
246 #define EMC_DLL_XFORM_DQ5 0x4e4
247 #define EMC_DLL_XFORM_DQ6 0x4e8
248 #define EMC_DLL_XFORM_DQ7 0x4ec
249 #define EMC_DLI_TRIM_TXDQS8 0x520
250 #define EMC_DLI_TRIM_TXDQS9 0x524
251 #define EMC_DLI_TRIM_TXDQS10 0x528
252 #define EMC_DLI_TRIM_TXDQS11 0x52c
253 #define EMC_DLI_TRIM_TXDQS12 0x530
254 #define EMC_DLI_TRIM_TXDQS13 0x534
255 #define EMC_DLI_TRIM_TXDQS14 0x538
256 #define EMC_DLI_TRIM_TXDQS15 0x53c
257 #define EMC_CDB_CNTL_3 0x540
258 #define EMC_XM2DQSPADCTRL5 0x544
259 #define EMC_XM2DQSPADCTRL6 0x548
260 #define EMC_XM2DQPADCTRL3 0x54c
261 #define EMC_DLL_XFORM_ADDR3 0x550
262 #define EMC_DLL_XFORM_ADDR4 0x554
263 #define EMC_DLL_XFORM_ADDR5 0x558
264 #define EMC_CFG_PIPE 0x560
265 #define EMC_QPOP 0x564
266 #define EMC_QUSE_WIDTH 0x568
267 #define EMC_PUTERM_WIDTH 0x56c
268 #define EMC_BGBIAS_CTL0 0x570
272 #define EMC_PUTERM_ADJ 0x574
274 #define DRAM_DEV_SEL_ALL 0
281 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
288 DRAM_TYPE_DDR3 = 0,
495 struct emc_timing *timings; member
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
532 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
534 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0) in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
549 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_disable_auto_cal()
550 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
551 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0) in emc_seq_disable_auto_cal()
556 dev_err(emc->dev, "auto cal disable timed out\n"); in emc_seq_disable_auto_cal()
559 static void emc_seq_wait_clkchange(struct tegra_emc *emc) in emc_seq_wait_clkchange() argument
564 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_wait_clkchange()
565 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
571 dev_err(emc->dev, "clock change timed out\n"); in emc_seq_wait_clkchange()
574 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
580 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
581 if (emc->timings[i].rate == rate) { in tegra_emc_find_timing()
582 timing = &emc->timings[i]; in tegra_emc_find_timing()
588 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
595 static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, in tegra_emc_prepare_timing_change() argument
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change()
599 struct emc_timing *last = &emc->last_timing; in tegra_emc_prepare_timing_change()
601 unsigned int pre_wait = 0; in tegra_emc_prepare_timing_change()
607 return -ENOENT; in tegra_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
611 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
619 /* Disable dynamic self-refresh */ in tegra_emc_prepare_timing_change()
620 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
623 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
641 val = readl(emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
642 val2 = last->emc_bgbias_ctl0; in tegra_emc_prepare_timing_change()
643 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
656 writel(val2, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
669 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
683 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
688 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
689 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
690 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
691 emc->regs + EMC_CTT_TERM_CTRL); in tegra_emc_prepare_timing_change()
692 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
696 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
697 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
698 emc->regs + emc_burst_regs[i]); in tegra_emc_prepare_timing_change()
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
706 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
709 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
713 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
717 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
718 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
720 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); in tegra_emc_prepare_timing_change()
724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
728 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
729 last->emc_zcal_interval == 0) in tegra_emc_prepare_timing_change()
730 cnt -= emc->dram_num * 256; in tegra_emc_prepare_timing_change()
732 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
738 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
743 writel(val, emc->regs + EMC_MRS_WAIT_CNT); in tegra_emc_prepare_timing_change()
746 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, val, EMC_CFG_2); in tegra_emc_prepare_timing_change()
750 /* DDR3: Turn off DLL and enter self-refresh */ in tegra_emc_prepare_timing_change()
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
755 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
758 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
763 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in tegra_emc_prepare_timing_change()
765 /* DDR3: Exit self-refresh */ in tegra_emc_prepare_timing_change()
766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
767 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
769 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
775 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
777 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
780 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
782 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
789 emc_ccfifo_writel(emc, val, EMC_MRS); in tegra_emc_prepare_timing_change()
792 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
794 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
796 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
801 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
802 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); in tegra_emc_prepare_timing_change()
803 if (emc->dram_num > 1) in tegra_emc_prepare_timing_change()
804 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1, in tegra_emc_prepare_timing_change()
809 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); in tegra_emc_prepare_timing_change()
811 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
815 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
818 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
820 return 0; in tegra_emc_prepare_timing_change()
823 static void tegra_emc_complete_timing_change(struct tegra_emc *emc, in tegra_emc_complete_timing_change() argument
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change()
827 struct emc_timing *last = &emc->last_timing; in tegra_emc_complete_timing_change()
834 emc_seq_wait_clkchange(emc); in tegra_emc_complete_timing_change()
837 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
838 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
839 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
841 /* Restore dynamic self-refresh */ in tegra_emc_complete_timing_change()
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
850 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
852 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
855 writel(val, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
858 readl(emc->regs + EMC_BGBIAS_CTL0) != in tegra_emc_complete_timing_change()
859 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
860 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
861 emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
864 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
865 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
873 emc_seq_update_timing(emc); in tegra_emc_complete_timing_change()
875 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
880 static void emc_read_current_timing(struct tegra_emc *emc, in emc_read_current_timing() argument
885 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i) in emc_read_current_timing()
886 timing->emc_burst_data[i] = in emc_read_current_timing()
887 readl(emc->regs + emc_burst_regs[i]); in emc_read_current_timing()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
891 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
892 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
893 timing->emc_mode_1 = 0; in emc_read_current_timing()
894 timing->emc_mode_2 = 0; in emc_read_current_timing()
895 timing->emc_mode_4 = 0; in emc_read_current_timing()
896 timing->emc_mode_reset = 0; in emc_read_current_timing()
899 static int emc_init(struct tegra_emc *emc) in emc_init() argument
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
903 if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64) in emc_init()
904 emc->dram_bus_width = 64; in emc_init()
906 emc->dram_bus_width = 32; in emc_init()
908 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); in emc_init()
910 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_init()
911 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in emc_init()
913 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_init()
915 emc_read_current_timing(emc, &emc->last_timing); in emc_init()
917 return 0; in emc_init()
920 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
927 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", in load_one_timing_from_dt()
934 timing->rate = value; in load_one_timing_from_dt()
936 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
937 timing->emc_burst_data, in load_one_timing_from_dt()
938 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
940 dev_err(emc->dev, in load_one_timing_from_dt()
941 "timing %pOFn: failed to read emc burst data: %d\n", in load_one_timing_from_dt()
947 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
949 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
955 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") in load_one_timing_from_dt()
956 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") in load_one_timing_from_dt()
957 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") in load_one_timing_from_dt()
958 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
959 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") in load_one_timing_from_dt()
960 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
961 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") in load_one_timing_from_dt()
962 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") in load_one_timing_from_dt()
963 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
964 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
965 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") in load_one_timing_from_dt()
966 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
967 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt") in load_one_timing_from_dt()
968 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") in load_one_timing_from_dt()
969 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") in load_one_timing_from_dt()
970 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
971 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval") in load_one_timing_from_dt()
975 return 0; in load_one_timing_from_dt()
983 if (a->rate < b->rate) in cmp_timings()
984 return -1; in cmp_timings()
985 else if (a->rate == b->rate) in cmp_timings()
986 return 0; in cmp_timings()
991 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, in tegra_emc_load_timings_from_dt() argument
996 unsigned int i = 0; in tegra_emc_load_timings_from_dt()
999 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
1001 if (!emc->timings) in tegra_emc_load_timings_from_dt()
1002 return -ENOMEM; in tegra_emc_load_timings_from_dt()
1004 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
1007 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
1009 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
1014 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
1017 return 0; in tegra_emc_load_timings_from_dt()
1021 { .compatible = "nvidia,tegra124-emc" },
1022 { .compatible = "nvidia,tegra132-emc" },
1036 err = of_property_read_u32(np, "nvidia,ram-code", &value); in tegra_emc_find_node_by_ram_code()
1046 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
1050 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { in tegra_emc_rate_requests_init()
1051 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
1052 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
1056 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
1061 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
1062 unsigned long min_rate = 0, max_rate = ULONG_MAX; in emc_request_rate()
1067 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { in emc_request_rate()
1072 min_rate = max(req->min_rate, min_rate); in emc_request_rate()
1073 max_rate = min(req->max_rate, max_rate); in emc_request_rate()
1078 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
1080 return -ERANGE; in emc_request_rate()
1084 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
1087 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
1091 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
1092 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
1094 return 0; in emc_request_rate()
1097 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
1100 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
1103 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
1104 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
1105 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
1110 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
1113 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
1116 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
1117 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
1118 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
1127 * to control the EMC frequency. The top-level directory can be found here:
1129 * /sys/kernel/debug/emc
1133 * - available_rates: This file contains a list of valid, space-separated
1134 * EMC frequencies.
1136 * - min_rate: Writing a value to this file sets the given frequency as the
1138 * configured EMC frequency, this will cause the frequency to be
1141 * - max_rate: Similarily to the min_rate file, writing a value to this file
1143 * the value is lower than the currently configured EMC frequency, this
1148 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1152 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1153 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1162 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1166 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1167 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1173 return 0; in tegra_emc_debug_available_rates_show()
1180 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1182 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1184 return 0; in tegra_emc_debug_min_rate_get()
1189 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1192 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1193 return -EINVAL; in tegra_emc_debug_min_rate_set()
1195 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
1196 if (err < 0) in tegra_emc_debug_min_rate_set()
1199 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1201 return 0; in tegra_emc_debug_min_rate_set()
1210 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1212 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1214 return 0; in tegra_emc_debug_max_rate_get()
1219 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1222 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1223 return -EINVAL; in tegra_emc_debug_max_rate_set()
1225 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
1226 if (err < 0) in tegra_emc_debug_max_rate_set()
1229 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1231 return 0; in tegra_emc_debug_max_rate_set()
1238 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) in emc_debugfs_init() argument
1243 emc->debugfs.min_rate = ULONG_MAX; in emc_debugfs_init()
1244 emc->debugfs.max_rate = 0; in emc_debugfs_init()
1246 for (i = 0; i < emc->num_timings; i++) { in emc_debugfs_init()
1247 if (emc->timings[i].rate < emc->debugfs.min_rate) in emc_debugfs_init()
1248 emc->debugfs.min_rate = emc->timings[i].rate; in emc_debugfs_init()
1250 if (emc->timings[i].rate > emc->debugfs.max_rate) in emc_debugfs_init()
1251 emc->debugfs.max_rate = emc->timings[i].rate; in emc_debugfs_init()
1254 if (!emc->num_timings) { in emc_debugfs_init()
1255 emc->debugfs.min_rate = clk_get_rate(emc->clk); in emc_debugfs_init()
1256 emc->debugfs.max_rate = emc->debugfs.min_rate; in emc_debugfs_init()
1259 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in emc_debugfs_init()
1260 emc->debugfs.max_rate); in emc_debugfs_init()
1261 if (err < 0) { in emc_debugfs_init()
1262 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in emc_debugfs_init()
1263 emc->debugfs.min_rate, emc->debugfs.max_rate, in emc_debugfs_init()
1264 emc->clk); in emc_debugfs_init()
1268 emc->debugfs.root = debugfs_create_dir("emc", NULL); in emc_debugfs_init()
1270 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in emc_debugfs_init()
1272 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1273 emc, &tegra_emc_debug_min_rate_fops); in emc_debugfs_init()
1274 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1275 emc, &tegra_emc_debug_max_rate_fops); in emc_debugfs_init()
1292 list_for_each_entry(node, &provider->nodes, node_list) { in emc_of_icc_xlate_extended()
1293 if (node->id != TEGRA_ICC_EMEM) in emc_of_icc_xlate_extended()
1298 return ERR_PTR(-ENOMEM); in emc_of_icc_xlate_extended()
1304 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in emc_of_icc_xlate_extended()
1305 ndata->node = node; in emc_of_icc_xlate_extended()
1310 return ERR_PTR(-EPROBE_DEFER); in emc_of_icc_xlate_extended()
1315 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
1316 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); in emc_icc_set()
1317 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); in emc_icc_set()
1324 * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that in emc_icc_set()
1325 * EMC clock rate is twice smaller than the peak data rate because in emc_icc_set()
1326 * data is sampled on both EMC clock edges. in emc_icc_set()
1328 dram_data_bus_width_bytes = emc->dram_bus_width / 8; in emc_icc_set()
1332 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
1336 return 0; in emc_icc_set()
1339 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
1341 const struct tegra_mc_soc *soc = emc->mc->soc; in tegra_emc_interconnect_init()
1345 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1346 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1347 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1348 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1349 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1351 icc_provider_init(&emc->provider); in tegra_emc_interconnect_init()
1360 node->name = "External Memory Controller"; in tegra_emc_interconnect_init()
1361 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1375 node->name = "External Memory (DRAM)"; in tegra_emc_interconnect_init()
1376 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1378 err = icc_provider_register(&emc->provider); in tegra_emc_interconnect_init()
1382 return 0; in tegra_emc_interconnect_init()
1385 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1387 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1392 static int tegra_emc_opp_table_init(struct tegra_emc *emc) in tegra_emc_opp_table_init() argument
1397 err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); in tegra_emc_opp_table_init()
1398 if (err < 0) { in tegra_emc_opp_table_init()
1399 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); in tegra_emc_opp_table_init()
1404 err = dev_pm_opp_of_add_table(emc->dev); in tegra_emc_opp_table_init()
1406 if (err == -ENODEV) in tegra_emc_opp_table_init()
1407 dev_err(emc->dev, "OPP table not found, please update your device tree\n"); in tegra_emc_opp_table_init()
1409 dev_err(emc->dev, "failed to add OPP table: %d\n", err); in tegra_emc_opp_table_init()
1414 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", in tegra_emc_opp_table_init()
1415 hw_version, clk_get_rate(emc->clk) / 1000000); in tegra_emc_opp_table_init()
1417 /* first dummy rate-set initializes voltage state */ in tegra_emc_opp_table_init()
1418 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); in tegra_emc_opp_table_init()
1420 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); in tegra_emc_opp_table_init()
1424 return 0; in tegra_emc_opp_table_init()
1427 dev_pm_opp_of_remove_table(emc->dev); in tegra_emc_opp_table_init()
1442 struct tegra_emc *emc; in tegra_emc_probe() local
1446 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1447 if (!emc) in tegra_emc_probe()
1448 return -ENOMEM; in tegra_emc_probe()
1450 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1451 emc->dev = &pdev->dev; in tegra_emc_probe()
1453 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1454 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1455 return PTR_ERR(emc->regs); in tegra_emc_probe()
1457 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra_emc_probe()
1458 if (IS_ERR(emc->mc)) in tegra_emc_probe()
1459 return PTR_ERR(emc->mc); in tegra_emc_probe()
1463 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code); in tegra_emc_probe()
1465 err = tegra_emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1470 dev_info_once(&pdev->dev, in tegra_emc_probe()
1471 "no memory timings for RAM code %u found in DT\n", in tegra_emc_probe()
1475 err = emc_init(emc); in tegra_emc_probe()
1477 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err); in tegra_emc_probe()
1481 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1486 err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback, in tegra_emc_probe()
1491 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra_emc_probe()
1492 if (IS_ERR(emc->clk)) { in tegra_emc_probe()
1493 err = PTR_ERR(emc->clk); in tegra_emc_probe()
1494 dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err); in tegra_emc_probe()
1498 err = tegra_emc_opp_table_init(emc); in tegra_emc_probe()
1502 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1505 emc_debugfs_init(&pdev->dev, emc); in tegra_emc_probe()
1507 tegra_emc_interconnect_init(emc); in tegra_emc_probe()
1516 return 0; in tegra_emc_probe()
1522 .name = "tegra-emc",
1531 MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");