Lines Matching +full:0 +full:x4e
15 .id = 0x00,
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
27 .id = 0x01,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
39 .def = 0x4e,
43 .id = 0x02,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
54 .mask = 0xff,
55 .def = 0x4e,
59 .id = 0x03,
64 .reg = 0x228,
68 .reg = 0x2e8,
70 .mask = 0xff,
71 .def = 0x4e,
75 .id = 0x04,
80 .reg = 0x228,
84 .reg = 0x2f4,
86 .mask = 0xff,
87 .def = 0x4e,
91 .id = 0x05,
96 .reg = 0x228,
100 .reg = 0x2ec,
101 .shift = 0,
102 .mask = 0xff,
103 .def = 0x4e,
107 .id = 0x06,
112 .reg = 0x228,
116 .reg = 0x2f8,
117 .shift = 0,
118 .mask = 0xff,
119 .def = 0x4e,
123 .id = 0x09,
128 .reg = 0x228,
132 .reg = 0x300,
133 .shift = 0,
134 .mask = 0xff,
135 .def = 0x33,
139 .id = 0x0a,
144 .reg = 0x228,
148 .reg = 0x308,
149 .shift = 0,
150 .mask = 0xff,
151 .def = 0x09,
155 .id = 0x0b,
160 .reg = 0x228,
164 .reg = 0x308,
166 .mask = 0xff,
167 .def = 0x09,
171 .id = 0x0f,
176 .reg = 0x228,
180 .reg = 0x2e4,
181 .shift = 0,
182 .mask = 0xff,
183 .def = 0x04,
187 .id = 0x10,
192 .reg = 0x228,
196 .reg = 0x2f0,
197 .shift = 0,
198 .mask = 0xff,
199 .def = 0x68,
203 .id = 0x11,
208 .reg = 0x228,
212 .reg = 0x2fc,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x68,
219 .id = 0x12,
224 .reg = 0x228,
228 .reg = 0x334,
229 .shift = 0,
230 .mask = 0xff,
231 .def = 0x0c,
235 .id = 0x13,
240 .reg = 0x228,
244 .reg = 0x33c,
245 .shift = 0,
246 .mask = 0xff,
247 .def = 0x0c,
251 .id = 0x14,
256 .reg = 0x228,
260 .reg = 0x30c,
261 .shift = 0,
262 .mask = 0xff,
263 .def = 0x0a,
267 .id = 0x15,
272 .reg = 0x228,
276 .reg = 0x318,
277 .shift = 0,
278 .mask = 0xff,
279 .def = 0xff,
283 .id = 0x16,
288 .reg = 0x228,
292 .reg = 0x310,
293 .shift = 0,
294 .mask = 0xff,
295 .def = 0x10,
299 .id = 0x17,
304 .reg = 0x228,
308 .reg = 0x310,
310 .mask = 0xff,
311 .def = 0xa5,
315 .id = 0x18,
320 .reg = 0x228,
324 .reg = 0x334,
326 .mask = 0xff,
327 .def = 0x0b,
331 .id = 0x1c,
336 .reg = 0x228,
340 .reg = 0x328,
341 .shift = 0,
342 .mask = 0xff,
343 .def = 0x80,
347 .id = 0x1d,
352 .reg = 0x228,
356 .reg = 0x344,
357 .shift = 0,
358 .mask = 0xff,
359 .def = 0x50,
363 .id = 0x1e,
368 .reg = 0x228,
372 .reg = 0x344,
374 .mask = 0xff,
375 .def = 0xe8,
379 .id = 0x20,
384 .reg = 0x22c,
385 .bit = 0,
388 .reg = 0x338,
389 .shift = 0,
390 .mask = 0xff,
391 .def = 0x0c,
395 .id = 0x22,
400 .reg = 0x22c,
404 .reg = 0x354,
405 .shift = 0,
406 .mask = 0xff,
407 .def = 0xff,
411 .id = 0x23,
416 .reg = 0x22c,
420 .reg = 0x354,
422 .mask = 0xff,
423 .def = 0xff,
427 .id = 0x24,
432 .reg = 0x22c,
436 .reg = 0x358,
437 .shift = 0,
438 .mask = 0xff,
439 .def = 0xb8,
443 .id = 0x25,
448 .reg = 0x22c,
452 .reg = 0x358,
454 .mask = 0xff,
455 .def = 0xee,
459 .id = 0x26,
464 .reg = 0x324,
465 .shift = 0,
466 .mask = 0xff,
467 .def = 0x04,
471 .id = 0x27,
476 .reg = 0x320,
477 .shift = 0,
478 .mask = 0xff,
479 .def = 0x04,
483 .id = 0x28,
488 .reg = 0x22c,
492 .reg = 0x300,
494 .mask = 0xff,
495 .def = 0x33,
499 .id = 0x29,
504 .reg = 0x22c,
508 .reg = 0x304,
509 .shift = 0,
510 .mask = 0xff,
511 .def = 0x6c,
515 .id = 0x2a,
520 .reg = 0x22c,
524 .reg = 0x304,
526 .mask = 0xff,
527 .def = 0x6c,
531 .id = 0x2b,
536 .reg = 0x22c,
540 .reg = 0x328,
542 .mask = 0xff,
543 .def = 0x80,
547 .id = 0x2c,
552 .reg = 0x22c,
556 .reg = 0x364,
557 .shift = 0,
558 .mask = 0xff,
559 .def = 0x47,
563 .id = 0x2d,
568 .reg = 0x22c,
572 .reg = 0x368,
573 .shift = 0,
574 .mask = 0xff,
575 .def = 0xff,
579 .id = 0x2e,
584 .reg = 0x22c,
588 .reg = 0x368,
590 .mask = 0xff,
591 .def = 0xff,
595 .id = 0x2f,
600 .reg = 0x22c,
604 .reg = 0x36c,
605 .shift = 0,
606 .mask = 0xff,
607 .def = 0x47,
611 .id = 0x30,
616 .reg = 0x22c,
620 .reg = 0x30c,
622 .mask = 0xff,
623 .def = 0x9,
627 .id = 0x32,
632 .reg = 0x22c,
636 .reg = 0x2e4,
638 .mask = 0xff,
639 .def = 0x0e,
643 .id = 0x33,
648 .reg = 0x22c,
652 .reg = 0x338,
654 .mask = 0xff,
655 .def = 0x10,
659 .id = 0x34,
664 .reg = 0x22c,
668 .reg = 0x340,
669 .shift = 0,
670 .mask = 0xff,
671 .def = 0x10,
675 .id = 0x35,
680 .reg = 0x22c,
684 .reg = 0x318,
686 .mask = 0xff,
687 .def = 0xff,
691 .id = 0x36,
696 .reg = 0x22c,
700 .reg = 0x314,
701 .shift = 0,
702 .mask = 0xff,
703 .def = 0x25,
707 .id = 0x37,
712 .reg = 0x22c,
716 .reg = 0x31c,
717 .shift = 0,
718 .mask = 0xff,
719 .def = 0xff,
723 .id = 0x38,
728 .reg = 0x324,
730 .mask = 0xff,
731 .def = 0x80,
735 .id = 0x39,
740 .reg = 0x320,
742 .mask = 0xff,
743 .def = 0x0e,
747 .id = 0x3b,
752 .reg = 0x22c,
756 .reg = 0x348,
757 .shift = 0,
758 .mask = 0xff,
759 .def = 0xa5,
763 .id = 0x3c,
768 .reg = 0x22c,
772 .reg = 0x348,
774 .mask = 0xff,
775 .def = 0xe8,
779 .id = 0x3e,
784 .reg = 0x22c,
788 .reg = 0x35c,
789 .shift = 0,
790 .mask = 0xff,
791 .def = 0xff,
795 .id = 0x3f,
800 .reg = 0x22c,
804 .reg = 0x35c,
806 .mask = 0xff,
807 .def = 0xff,
811 .id = 0x40,
816 .reg = 0x230,
817 .bit = 0,
820 .reg = 0x360,
821 .shift = 0,
822 .mask = 0xff,
823 .def = 0x89,
827 .id = 0x41,
832 .reg = 0x230,
836 .reg = 0x360,
838 .mask = 0xff,
839 .def = 0x59,
843 .id = 0x4a,
848 .reg = 0x230,
852 .reg = 0x37c,
853 .shift = 0,
854 .mask = 0xff,
855 .def = 0xa5,
859 .id = 0x4b,
864 .reg = 0x230,
868 .reg = 0x37c,
870 .mask = 0xff,
871 .def = 0xa5,
875 .id = 0x4c,
880 .reg = 0x230,
884 .reg = 0x380,
885 .shift = 0,
886 .mask = 0xff,
887 .def = 0xa5,
891 .id = 0x4d,
896 .reg = 0x230,
900 .reg = 0x380,
902 .mask = 0xff,
903 .def = 0xa5,
907 .id = 0x4e,
912 .reg = 0x230,
916 .reg = 0x388,
917 .shift = 0,
918 .mask = 0xff,
919 .def = 0x10,
923 .id = 0x4f,
928 .reg = 0x230,
932 .reg = 0x384,
933 .shift = 0,
934 .mask = 0xff,
935 .def = 0x0c,
939 .id = 0x50,
944 .reg = 0x230,
948 .reg = 0x388,
950 .mask = 0xff,
951 .def = 0x10,
955 .id = 0x51,
960 .reg = 0x230,
964 .reg = 0x384,
966 .mask = 0xff,
967 .def = 0x0c,
971 .id = 0x52,
976 .reg = 0x38c,
977 .shift = 0,
978 .mask = 0xff,
979 .def = 0x04,
983 .id = 0x53,
988 .reg = 0x38c,
990 .mask = 0xff,
991 .def = 0x0e,
995 .id = 0x54,
1000 .reg = 0x230,
1004 .reg = 0x390,
1005 .shift = 0,
1006 .mask = 0xff,
1007 .def = 0x50,
1011 .id = 0x55,
1016 .reg = 0x230,
1020 .reg = 0x390,
1022 .mask = 0xff,
1023 .def = 0x50,
1030 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1031 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1032 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1033 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1036 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1037 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1038 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1039 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1040 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1041 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1042 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1043 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1045 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1086 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
1087 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
1088 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
1089 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
1090 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
1091 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
1092 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
1093 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
1094 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
1095 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1096 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
1097 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
1098 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
1099 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
1101 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
1109 .client_id_mask = 0x7f,