Lines Matching +full:tegra124 +full:- +full:mc
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
22 #include "mc.h"
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
44 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
47 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
50 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
58 struct tegra_mc *mc = data; in tegra_mc_devm_action_put_device() local
60 put_device(mc->dev); in tegra_mc_devm_action_put_device()
64 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle
67 * This function will search for the Memory Controller node in a device-tree
76 struct tegra_mc *mc; in devm_tegra_memory_controller_get() local
79 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); in devm_tegra_memory_controller_get()
81 return ERR_PTR(-ENOENT); in devm_tegra_memory_controller_get()
86 return ERR_PTR(-ENODEV); in devm_tegra_memory_controller_get()
88 mc = platform_get_drvdata(pdev); in devm_tegra_memory_controller_get()
89 if (!mc) { in devm_tegra_memory_controller_get()
90 put_device(&pdev->dev); in devm_tegra_memory_controller_get()
91 return ERR_PTR(-EPROBE_DEFER); in devm_tegra_memory_controller_get()
94 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); in devm_tegra_memory_controller_get()
98 return mc; in devm_tegra_memory_controller_get()
102 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) in tegra_mc_probe_device() argument
104 if (mc->soc->ops && mc->soc->ops->probe_device) in tegra_mc_probe_device()
105 return mc->soc->ops->probe_device(mc, dev); in tegra_mc_probe_device()
111 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, in tegra_mc_get_carveout_info() argument
116 if (id < 1 || id >= mc->soc->num_carveouts) in tegra_mc_get_carveout_info()
117 return -EINVAL; in tegra_mc_get_carveout_info()
120 offset = 0xc0c + 0x50 * (id - 1); in tegra_mc_get_carveout_info()
122 offset = 0x2004 + 0x50 * (id - 6); in tegra_mc_get_carveout_info()
124 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0); in tegra_mc_get_carveout_info()
126 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32; in tegra_mc_get_carveout_info()
130 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17; in tegra_mc_get_carveout_info()
136 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument
142 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
144 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
145 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
147 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_block_dma_common()
152 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, in tegra_mc_dma_idling_common() argument
155 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
158 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, in tegra_mc_unblock_dma_common() argument
164 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_unblock_dma_common()
166 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
167 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
169 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_unblock_dma_common()
174 static int tegra_mc_reset_status_common(struct tegra_mc *mc, in tegra_mc_reset_status_common() argument
177 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
192 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, in tegra_mc_reset_find() argument
197 for (i = 0; i < mc->soc->num_resets; i++) in tegra_mc_reset_find()
198 if (mc->soc->resets[i].id == id) in tegra_mc_reset_find()
199 return &mc->soc->resets[i]; in tegra_mc_reset_find()
207 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_assert() local
213 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_assert()
215 return -ENODEV; in tegra_mc_hotreset_assert()
217 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_assert()
219 return -ENODEV; in tegra_mc_hotreset_assert()
222 if (rst_ops->reset_status) { in tegra_mc_hotreset_assert()
224 if (rst_ops->reset_status(mc, rst)) in tegra_mc_hotreset_assert()
228 if (rst_ops->block_dma) { in tegra_mc_hotreset_assert()
230 err = rst_ops->block_dma(mc, rst); in tegra_mc_hotreset_assert()
232 dev_err(mc->dev, "failed to block %s DMA: %d\n", in tegra_mc_hotreset_assert()
233 rst->name, err); in tegra_mc_hotreset_assert()
238 if (rst_ops->dma_idling) { in tegra_mc_hotreset_assert()
240 while (!rst_ops->dma_idling(mc, rst)) { in tegra_mc_hotreset_assert()
241 if (!retries--) { in tegra_mc_hotreset_assert()
242 dev_err(mc->dev, "failed to flush %s DMA\n", in tegra_mc_hotreset_assert()
243 rst->name); in tegra_mc_hotreset_assert()
244 return -EBUSY; in tegra_mc_hotreset_assert()
251 if (rst_ops->hotreset_assert) { in tegra_mc_hotreset_assert()
253 err = rst_ops->hotreset_assert(mc, rst); in tegra_mc_hotreset_assert()
255 dev_err(mc->dev, "failed to hot reset %s: %d\n", in tegra_mc_hotreset_assert()
256 rst->name, err); in tegra_mc_hotreset_assert()
267 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_deassert() local
272 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_deassert()
274 return -ENODEV; in tegra_mc_hotreset_deassert()
276 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_deassert()
278 return -ENODEV; in tegra_mc_hotreset_deassert()
280 if (rst_ops->hotreset_deassert) { in tegra_mc_hotreset_deassert()
282 err = rst_ops->hotreset_deassert(mc, rst); in tegra_mc_hotreset_deassert()
284 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", in tegra_mc_hotreset_deassert()
285 rst->name, err); in tegra_mc_hotreset_deassert()
290 if (rst_ops->unblock_dma) { in tegra_mc_hotreset_deassert()
292 err = rst_ops->unblock_dma(mc, rst); in tegra_mc_hotreset_deassert()
294 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", in tegra_mc_hotreset_deassert()
295 rst->name, err); in tegra_mc_hotreset_deassert()
306 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_status() local
310 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_status()
312 return -ENODEV; in tegra_mc_hotreset_status()
314 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_status()
316 return -ENODEV; in tegra_mc_hotreset_status()
318 return rst_ops->reset_status(mc, rst); in tegra_mc_hotreset_status()
327 static int tegra_mc_reset_setup(struct tegra_mc *mc) in tegra_mc_reset_setup() argument
331 mc->reset.ops = &tegra_mc_reset_ops; in tegra_mc_reset_setup()
332 mc->reset.owner = THIS_MODULE; in tegra_mc_reset_setup()
333 mc->reset.of_node = mc->dev->of_node; in tegra_mc_reset_setup()
334 mc->reset.of_reset_n_cells = 1; in tegra_mc_reset_setup()
335 mc->reset.nr_resets = mc->soc->num_resets; in tegra_mc_reset_setup()
337 err = reset_controller_register(&mc->reset); in tegra_mc_reset_setup()
344 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) in tegra_mc_write_emem_configuration() argument
349 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
350 if (mc->timings[i].rate == rate) { in tegra_mc_write_emem_configuration()
351 timing = &mc->timings[i]; in tegra_mc_write_emem_configuration()
357 dev_err(mc->dev, "no memory timing registered for rate %lu\n", in tegra_mc_write_emem_configuration()
359 return -EINVAL; in tegra_mc_write_emem_configuration()
362 for (i = 0; i < mc->soc->num_emem_regs; ++i) in tegra_mc_write_emem_configuration()
363 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
369 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) in tegra_mc_get_emem_device_count() argument
373 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); in tegra_mc_get_emem_device_count()
386 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) in tegra_mc_setup_latency_allowance() argument
392 /* compute the number of MC clock cycles per tick */ in tegra_mc_setup_latency_allowance()
393 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); in tegra_mc_setup_latency_allowance()
396 value = mc_readl(mc, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
399 mc_writel(mc, value, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
402 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_setup_latency_allowance()
403 const struct tegra_mc_client *client = &mc->soc->clients[i]; in tegra_mc_setup_latency_allowance()
406 value = mc_readl(mc, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
407 value &= ~(client->regs.la.mask << client->regs.la.shift); in tegra_mc_setup_latency_allowance()
408 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; in tegra_mc_setup_latency_allowance()
409 mc_writel(mc, value, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
413 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in tegra_mc_setup_latency_allowance()
418 static int load_one_timing(struct tegra_mc *mc, in load_one_timing() argument
425 err = of_property_read_u32(node, "clock-frequency", &tmp); in load_one_timing()
427 dev_err(mc->dev, in load_one_timing()
432 timing->rate = tmp; in load_one_timing()
433 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, in load_one_timing()
435 if (!timing->emem_data) in load_one_timing()
436 return -ENOMEM; in load_one_timing()
438 err = of_property_read_u32_array(node, "nvidia,emem-configuration", in load_one_timing()
439 timing->emem_data, in load_one_timing()
440 mc->soc->num_emem_regs); in load_one_timing()
442 dev_err(mc->dev, in load_one_timing()
451 static int load_timings(struct tegra_mc *mc, struct device_node *node) in load_timings() argument
457 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), in load_timings()
459 if (!mc->timings) in load_timings()
460 return -ENOMEM; in load_timings()
462 mc->num_timings = child_count; in load_timings()
465 timing = &mc->timings[i++]; in load_timings()
467 err = load_one_timing(mc, timing, child); in load_timings()
475 static int tegra_mc_setup_timings(struct tegra_mc *mc) in tegra_mc_setup_timings() argument
482 mc->num_timings = 0; in tegra_mc_setup_timings()
484 for_each_child_of_node_scoped(mc->dev->of_node, node) { in tegra_mc_setup_timings()
485 err = of_property_read_u32(node, "nvidia,ram-code", in tegra_mc_setup_timings()
490 err = load_timings(mc, node); in tegra_mc_setup_timings()
496 if (mc->num_timings == 0) in tegra_mc_setup_timings()
497 dev_warn(mc->dev, in tegra_mc_setup_timings()
504 int tegra30_mc_probe(struct tegra_mc *mc) in tegra30_mc_probe() argument
508 mc->clk = devm_clk_get_optional(mc->dev, "mc"); in tegra30_mc_probe()
509 if (IS_ERR(mc->clk)) { in tegra30_mc_probe()
510 dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk)); in tegra30_mc_probe()
511 return PTR_ERR(mc->clk); in tegra30_mc_probe()
515 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); in tegra30_mc_probe()
517 err = tegra_mc_setup_latency_allowance(mc); in tegra30_mc_probe()
519 dev_err(mc->dev, "failed to setup latency allowance: %d\n", err); in tegra30_mc_probe()
523 err = tegra_mc_setup_timings(mc); in tegra30_mc_probe()
525 dev_err(mc->dev, "failed to setup timings: %d\n", err); in tegra30_mc_probe()
538 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, in mc_global_intstatus_to_channel() argument
541 if ((status & mc->soc->ch_intmask) == 0) in mc_global_intstatus_to_channel()
542 return -EINVAL; in mc_global_intstatus_to_channel()
544 *mc_channel = __ffs((status & mc->soc->ch_intmask) >> in mc_global_intstatus_to_channel()
545 mc->soc->global_intstatus_channel_shift); in mc_global_intstatus_to_channel()
550 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, in mc_channel_to_global_intstatus() argument
553 return BIT(channel) << mc->soc->global_intstatus_channel_shift; in mc_channel_to_global_intstatus()
558 struct tegra_mc *mc = data; in tegra30_mc_handle_irq() local
562 if (mc->soc->num_channels) { in tegra30_mc_handle_irq()
566 global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); in tegra30_mc_handle_irq()
567 err = mc_global_intstatus_to_channel(mc, global_status, &channel); in tegra30_mc_handle_irq()
569 dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", in tegra30_mc_handle_irq()
575 status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; in tegra30_mc_handle_irq()
577 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra30_mc_handle_irq()
629 if (mc->soc->has_addr_hi_reg) in tegra30_mc_handle_irq()
635 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
636 value = mc_ch_readl(mc, channel, status_reg); in tegra30_mc_handle_irq()
638 value = mc_readl(mc, status_reg); in tegra30_mc_handle_irq()
641 if (mc->soc->num_address_bits > 32) { in tegra30_mc_handle_irq()
643 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
644 addr = mc_ch_readl(mc, channel, addr_hi_reg); in tegra30_mc_handle_irq()
646 addr = mc_readl(mc, addr_hi_reg); in tegra30_mc_handle_irq()
665 id = value & mc->soc->client_id_mask; in tegra30_mc_handle_irq()
667 for (i = 0; i < mc->soc->num_clients; i++) { in tegra30_mc_handle_irq()
668 if (mc->soc->clients[i].id == id) { in tegra30_mc_handle_irq()
669 client = mc->soc->clients[i].name; in tegra30_mc_handle_irq()
686 perm[2] = '-'; in tegra30_mc_handle_irq()
691 perm[3] = '-'; in tegra30_mc_handle_irq()
694 perm[4] = '-'; in tegra30_mc_handle_irq()
707 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
708 value = mc_ch_readl(mc, channel, addr_reg); in tegra30_mc_handle_irq()
710 value = mc_readl(mc, addr_reg); in tegra30_mc_handle_irq()
713 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", in tegra30_mc_handle_irq()
719 if (mc->soc->num_channels) { in tegra30_mc_handle_irq()
720 mc_ch_writel(mc, channel, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
721 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, in tegra30_mc_handle_irq()
722 mc_channel_to_global_intstatus(mc, channel), in tegra30_mc_handle_irq()
725 mc_writel(mc, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
755 struct tegra_mc *mc = icc_provider_to_tegra_mc(data); in tegra_mc_icc_xlate() local
758 list_for_each_entry(node, &mc->provider.nodes, node_list) { in tegra_mc_icc_xlate()
759 if (node->id == spec->args[0]) in tegra_mc_icc_xlate()
764 * If a client driver calls devm_of_icc_get() before the MC driver in tegra_mc_icc_xlate()
767 return ERR_PTR(-EPROBE_DEFER); in tegra_mc_icc_xlate()
791 * Memory Controller (MC) has few Memory Clients that are issuing memory
792 * bandwidth allocation requests to the MC interconnect provider. The MC
795 * re-configures hardware interface to External Memory (EMEM) in accordance
796 * to the required bandwidth. Each MC interconnect node represents an
801 * +----+
802 * +--------+ | |
803 * | TEXSRD +--->+ |
804 * +--------+ | |
805 * | | +-----+ +------+
806 * ... | MC +--->+ EMC +--->+ EMEM |
807 * | | +-----+ +------+
808 * +--------+ | |
809 * | DISP.. +--->+ |
810 * +--------+ | |
811 * +----+
813 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) in tegra_mc_interconnect_setup() argument
819 /* older device-trees don't have interconnect properties */ in tegra_mc_interconnect_setup()
820 if (!device_property_present(mc->dev, "#interconnect-cells") || in tegra_mc_interconnect_setup()
821 !mc->soc->icc_ops) in tegra_mc_interconnect_setup()
824 mc->provider.dev = mc->dev; in tegra_mc_interconnect_setup()
825 mc->provider.data = &mc->provider; in tegra_mc_interconnect_setup()
826 mc->provider.set = mc->soc->icc_ops->set; in tegra_mc_interconnect_setup()
827 mc->provider.aggregate = mc->soc->icc_ops->aggregate; in tegra_mc_interconnect_setup()
828 mc->provider.get_bw = mc->soc->icc_ops->get_bw; in tegra_mc_interconnect_setup()
829 mc->provider.xlate = mc->soc->icc_ops->xlate; in tegra_mc_interconnect_setup()
830 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; in tegra_mc_interconnect_setup()
832 icc_provider_init(&mc->provider); in tegra_mc_interconnect_setup()
839 node->name = "Memory Controller"; in tegra_mc_interconnect_setup()
840 icc_node_add(node, &mc->provider); in tegra_mc_interconnect_setup()
847 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_interconnect_setup()
848 /* create MC client node */ in tegra_mc_interconnect_setup()
849 node = icc_node_create(mc->soc->clients[i].id); in tegra_mc_interconnect_setup()
855 node->name = mc->soc->clients[i].name; in tegra_mc_interconnect_setup()
856 icc_node_add(node, &mc->provider); in tegra_mc_interconnect_setup()
863 node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); in tegra_mc_interconnect_setup()
866 err = icc_provider_register(&mc->provider); in tegra_mc_interconnect_setup()
873 icc_nodes_remove(&mc->provider); in tegra_mc_interconnect_setup()
878 static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) in tegra_mc_num_channel_enabled() argument
883 value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE); in tegra_mc_num_channel_enabled()
885 mc->num_channels = mc->soc->num_channels; in tegra_mc_num_channel_enabled()
891 mc->num_channels++; in tegra_mc_num_channel_enabled()
897 struct tegra_mc *mc; in tegra_mc_probe() local
901 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); in tegra_mc_probe()
902 if (!mc) in tegra_mc_probe()
903 return -ENOMEM; in tegra_mc_probe()
905 platform_set_drvdata(pdev, mc); in tegra_mc_probe()
906 spin_lock_init(&mc->lock); in tegra_mc_probe()
907 mc->soc = of_device_get_match_data(&pdev->dev); in tegra_mc_probe()
908 mc->dev = &pdev->dev; in tegra_mc_probe()
910 mask = DMA_BIT_MASK(mc->soc->num_address_bits); in tegra_mc_probe()
912 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); in tegra_mc_probe()
914 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); in tegra_mc_probe()
918 /* length of MC tick in nanoseconds */ in tegra_mc_probe()
919 mc->tick = 30; in tegra_mc_probe()
921 mc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_mc_probe()
922 if (IS_ERR(mc->regs)) in tegra_mc_probe()
923 return PTR_ERR(mc->regs); in tegra_mc_probe()
925 mc->debugfs.root = debugfs_create_dir("mc", NULL); in tegra_mc_probe()
927 if (mc->soc->ops && mc->soc->ops->probe) { in tegra_mc_probe()
928 err = mc->soc->ops->probe(mc); in tegra_mc_probe()
933 tegra_mc_num_channel_enabled(mc); in tegra_mc_probe()
935 if (mc->soc->ops && mc->soc->ops->handle_irq) { in tegra_mc_probe()
936 mc->irq = platform_get_irq(pdev, 0); in tegra_mc_probe()
937 if (mc->irq < 0) in tegra_mc_probe()
938 return mc->irq; in tegra_mc_probe()
940 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); in tegra_mc_probe()
942 if (mc->soc->num_channels) in tegra_mc_probe()
943 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, in tegra_mc_probe()
946 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
948 err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, in tegra_mc_probe()
949 dev_name(&pdev->dev), mc); in tegra_mc_probe()
951 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, in tegra_mc_probe()
957 if (mc->soc->reset_ops) { in tegra_mc_probe()
958 err = tegra_mc_reset_setup(mc); in tegra_mc_probe()
960 dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); in tegra_mc_probe()
963 err = tegra_mc_interconnect_setup(mc); in tegra_mc_probe()
965 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", in tegra_mc_probe()
968 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { in tegra_mc_probe()
969 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); in tegra_mc_probe()
970 if (IS_ERR(mc->smmu)) { in tegra_mc_probe()
971 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", in tegra_mc_probe()
972 PTR_ERR(mc->smmu)); in tegra_mc_probe()
973 mc->smmu = NULL; in tegra_mc_probe()
982 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_sync_state() local
985 if (mc->provider.dev == dev) in tegra_mc_sync_state()
991 .name = "tegra-mc",