157 	void __iomem *base_drexi0;  member
389 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);  in exynos5_set_bypass_dram_timings()
392 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);  in exynos5_set_bypass_dram_timings()
396 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);  in exynos5_set_bypass_dram_timings()
400 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);  in exynos5_set_bypass_dram_timings()
429 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);  in exynos5_dram_change_timings()
432 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);  in exynos5_dram_change_timings()
436 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);  in exynos5_dram_change_timings()
440 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);  in exynos5_dram_change_timings()
768 	writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);  in exynos5_dmc_start_perf_events()
772 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);  in exynos5_dmc_start_perf_events()
776 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_start_perf_events()
780 	writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_start_perf_events()
787 	writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);  in exynos5_dmc_start_perf_events()
791 	writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_start_perf_events()
850 	writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_perf_events_check()
854 	val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_perf_events_check()
882 	writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);  in exynos5_dmc_enable_perf_events()
886 	writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);  in exynos5_dmc_enable_perf_events()
907 	writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_disable_perf_events()
911 	writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);  in exynos5_dmc_disable_perf_events()
915 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);  in exynos5_dmc_disable_perf_events()
919 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_disable_perf_events()
1429 	dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);  in exynos5_dmc_probe()
1430 	if (IS_ERR(dmc->base_drexi0))  in exynos5_dmc_probe()
1431 		return PTR_ERR(dmc->base_drexi0);  in exynos5_dmc_probe()