Lines Matching +full:emc +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
86 u32 cfg; in pl172_setup_static() local
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { in pl172_setup_static()
91 if (cfg == 8) { in pl172_setup_static()
92 cfg = MPMC_STATIC_CFG_MW_8BIT; in pl172_setup_static()
93 } else if (cfg == 16) { in pl172_setup_static()
94 cfg = MPMC_STATIC_CFG_MW_16BIT; in pl172_setup_static()
95 } else if (cfg == 32) { in pl172_setup_static()
96 cfg = MPMC_STATIC_CFG_MW_32BIT; in pl172_setup_static()
98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs); in pl172_setup_static()
99 return -EINVAL; in pl172_setup_static()
102 dev_err(&adev->dev, "memory-width property required\n"); in pl172_setup_static()
103 return -EINVAL; in pl172_setup_static()
106 if (of_property_read_bool(np, "mpmc,async-page-mode")) in pl172_setup_static()
107 cfg |= MPMC_STATIC_CFG_PM; in pl172_setup_static()
109 if (of_property_read_bool(np, "mpmc,cs-active-high")) in pl172_setup_static()
110 cfg |= MPMC_STATIC_CFG_PC; in pl172_setup_static()
112 if (of_property_read_bool(np, "mpmc,byte-lane-low")) in pl172_setup_static()
113 cfg |= MPMC_STATIC_CFG_PB; in pl172_setup_static()
115 if (of_property_read_bool(np, "mpmc,extended-wait")) in pl172_setup_static()
116 cfg |= MPMC_STATIC_CFG_EW; in pl172_setup_static()
119 of_property_read_bool(np, "mpmc,buffer-enable")) in pl172_setup_static()
120 cfg |= MPMC_STATIC_CFG_B; in pl172_setup_static()
122 if (of_property_read_bool(np, "mpmc,write-protect")) in pl172_setup_static()
123 cfg |= MPMC_STATIC_CFG_P; in pl172_setup_static()
125 writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); in pl172_setup_static()
126 dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg); in pl172_setup_static()
129 ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay", in pl172_setup_static()
135 ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay", in pl172_setup_static()
141 ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay", in pl172_setup_static()
147 ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay", in pl172_setup_static()
153 ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay", in pl172_setup_static()
159 ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay", in pl172_setup_static()
167 dev_err(&adev->dev, "failed to configure cs%u\n", cs); in pl172_setup_static()
178 dev_err(&adev->dev, "cs%u invalid\n", cs); in pl172_parse_cs_config()
179 return -EINVAL; in pl172_parse_cs_config()
185 dev_err(&adev->dev, "cs property required\n"); in pl172_parse_cs_config()
187 return -EINVAL; in pl172_parse_cs_config()
203 struct device_node *child_np, *np = adev->dev.of_node; in pl172_probe()
204 struct device *dev = &adev->dev; in pl172_probe()
224 return -ENOMEM; in pl172_probe()
226 pl172->clk = devm_clk_get_enabled(dev, "mpmcclk"); in pl172_probe()
227 if (IS_ERR(pl172->clk)) in pl172_probe()
228 return dev_err_probe(dev, PTR_ERR(pl172->clk), in pl172_probe()
231 pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC; in pl172_probe()
232 if (!pl172->rate) in pl172_probe()
233 return dev_err_probe(dev, -EINVAL, in pl172_probe()
246 pl172->base = devm_ioremap(dev, adev->res.start, in pl172_probe()
247 resource_size(&adev->res)); in pl172_probe()
248 if (!pl172->base) in pl172_probe()
249 return dev_err_probe(dev, -ENOMEM, "ioremap failed\n"); in pl172_probe()
270 /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
275 /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
291 .name = "memory-pl172",