Lines Matching +full:0 +full:x0e
15 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 in fc0012_writereg()
24 return 0; in fc0012_writereg()
30 { .addr = priv->cfg->i2c_address, .flags = 0, in fc0012_readreg()
42 return 0; in fc0012_readreg()
54 int i, ret = 0; in fc0012_init()
56 0x00, /* dummy reg. 0 */ in fc0012_init()
57 0x05, /* reg. 0x01 */ in fc0012_init()
58 0x10, /* reg. 0x02 */ in fc0012_init()
59 0x00, /* reg. 0x03 */ in fc0012_init()
60 0x00, /* reg. 0x04 */ in fc0012_init()
61 0x0f, /* reg. 0x05: may also be 0x0a */ in fc0012_init()
62 0x00, /* reg. 0x06: divider 2, VCO slow */ in fc0012_init()
63 0x00, /* reg. 0x07: may also be 0x0f */ in fc0012_init()
64 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, in fc0012_init()
66 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ in fc0012_init()
67 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ in fc0012_init()
68 0x82, /* reg. 0x0b: Output Clock is same as clock frequency, in fc0012_init()
69 may also be 0x83 */ in fc0012_init()
70 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ in fc0012_init()
71 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ in fc0012_init()
72 0x00, /* reg. 0x0e */ in fc0012_init()
73 0x00, /* reg. 0x0f */ in fc0012_init()
74 0x00, /* reg. 0x10: may also be 0x0d */ in fc0012_init()
75 0x00, /* reg. 0x11 */ in fc0012_init()
76 0x1f, /* reg. 0x12: Set to maximum gain */ in fc0012_init()
77 0x08, /* reg. 0x13: Set to Middle Gain: 0x08, in fc0012_init()
78 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */ in fc0012_init()
79 0x00, /* reg. 0x14 */ in fc0012_init()
80 0x04, /* reg. 0x15: Enable LNA COMPS */ in fc0012_init()
86 reg[0x07] |= 0x20; in fc0012_init()
94 reg[0x0c] |= 0x02; in fc0012_init()
97 reg[0x09] |= 0x01; in fc0012_init()
109 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0012_init()
121 int i, ret = 0; in fc0012_set_params()
132 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); in fc0012_set_params()
153 reg[5] = 0x82; in fc0012_set_params()
154 reg[6] = 0x00; in fc0012_set_params()
157 reg[5] = 0x82; in fc0012_set_params()
158 reg[6] = 0x02; in fc0012_set_params()
161 reg[5] = 0x42; in fc0012_set_params()
162 reg[6] = 0x00; in fc0012_set_params()
165 reg[5] = 0x42; in fc0012_set_params()
166 reg[6] = 0x02; in fc0012_set_params()
169 reg[5] = 0x22; in fc0012_set_params()
170 reg[6] = 0x00; in fc0012_set_params()
173 reg[5] = 0x22; in fc0012_set_params()
174 reg[6] = 0x02; in fc0012_set_params()
177 reg[5] = 0x12; in fc0012_set_params()
178 reg[6] = 0x00; in fc0012_set_params()
181 reg[5] = 0x12; in fc0012_set_params()
182 reg[6] = 0x02; in fc0012_set_params()
185 reg[5] = 0x0a; in fc0012_set_params()
186 reg[6] = 0x00; in fc0012_set_params()
189 reg[5] = 0x0a; in fc0012_set_params()
190 reg[6] = 0x02; in fc0012_set_params()
196 reg[6] |= 0x08; in fc0012_set_params()
218 reg[1] = 0x06; in fc0012_set_params()
219 reg[2] = 0x11; in fc0012_set_params()
223 reg[6] |= 0x20; in fc0012_set_params()
233 reg[4] = xin & 0xff; in fc0012_set_params()
236 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ in fc0012_set_params()
239 reg[6] |= 0x80; in fc0012_set_params()
242 reg[6] |= 0x40; in fc0012_set_params()
255 reg[5] |= 0x07; in fc0012_set_params()
267 ret = fc0012_writereg(priv, 0x0e, 0x80); in fc0012_set_params()
269 ret = fc0012_writereg(priv, 0x0e, 0x00); in fc0012_set_params()
273 ret = fc0012_writereg(priv, 0x0e, 0x00); in fc0012_set_params()
277 ret = fc0012_readreg(priv, 0x0e, &tmp); in fc0012_set_params()
283 tmp &= 0x3f; in fc0012_set_params()
286 if (tmp > 0x3c) { in fc0012_set_params()
287 reg[6] &= ~0x08; in fc0012_set_params()
288 ret = fc0012_writereg(priv, 0x06, reg[6]); in fc0012_set_params()
290 ret = fc0012_writereg(priv, 0x0e, 0x80); in fc0012_set_params()
292 ret = fc0012_writereg(priv, 0x0e, 0x00); in fc0012_set_params()
295 if (tmp < 0x02) { in fc0012_set_params()
296 reg[6] |= 0x08; in fc0012_set_params()
297 ret = fc0012_writereg(priv, 0x06, reg[6]); in fc0012_set_params()
299 ret = fc0012_writereg(priv, 0x0e, 0x80); in fc0012_set_params()
301 ret = fc0012_writereg(priv, 0x0e, 0x00); in fc0012_set_params()
310 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0012_set_params()
321 return 0; in fc0012_get_frequency()
326 *frequency = 0; /* Zero-IF */ in fc0012_get_if_frequency()
327 return 0; in fc0012_get_if_frequency()
334 return 0; in fc0012_get_bandwidth()
360 ret = fc0012_writereg(priv, 0x12, 0x00); in fc0012_get_rf_strength()
364 ret = fc0012_readreg(priv, 0x12, &tmp); in fc0012_get_rf_strength()
369 ret = fc0012_readreg(priv, 0x13, &tmp); in fc0012_get_rf_strength()
372 lna_gain = tmp & 0x1f; in fc0012_get_rf_strength()
375 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0012_get_rf_strength()
380 (int_temp & 0x1f)) * 2; in fc0012_get_rf_strength()
386 *strength = 0; in fc0012_get_rf_strength()
399 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0012_get_rf_strength()
449 ret = fc0012_readreg(priv, 0x00, &chip_id); in fc0012_attach()
450 if (ret < 0) in fc0012_attach()
456 case 0xa1: in fc0012_attach()
467 ret = fc0012_writereg(priv, 0x09, 0x6f); in fc0012_attach()
468 if (ret < 0) in fc0012_attach()
474 * For dual tuner configuration clearing bit [0] is required. in fc0012_attach()
477 ret = fc0012_writereg(priv, 0x0b, 0x82); in fc0012_attach()
478 if (ret < 0) in fc0012_attach()
488 fe->ops.i2c_gate_ctrl(fe, 0); in fc0012_attach()