Lines Matching +full:max +full:- +full:rx +full:- +full:timeout +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/rc-core.h>
24 void __iomem *rx_base;/* RX Register base address */
43 #define IRB_MAX_SYM_PERIOD 0x54 /* max sym value */
50 * IRQ set: Enable full FIFO 1 -> bit 3;
51 * Enable overrun IRQ 1 -> bit 2;
52 * Enable last symbol IRQ 1 -> bit 1:
53 * Enable RX interrupt 1 -> bit 0;
57 /* maximum symbol period (microsecs),timeout to detect end of symbol train */
63 #define IR_ST_NAME "st-rc"
67 struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout }; in st_rc_send_lirc_timeout()
72 * RX graphical example to better understand the difference between ST IR block
76 * |-IRB_RX_ON-| |-IRB_RX_ON-|
82 * |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------|
84 * |------------- encoding bit 0 -----------|---- encoding bit 1 -----|
87 * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark)
88 * The mark time represents the amount of time the carrier (usually 36-40kHz)
95 unsigned long timeout; in st_rc_rx_interrupt() local
102 if (dev->irq_wake) in st_rc_rx_interrupt()
103 pm_wakeup_event(dev->dev, 0); in st_rc_rx_interrupt()
105 /* FIXME: is 10ms good enough ? */ in st_rc_rx_interrupt()
106 timeout = jiffies + msecs_to_jiffies(10); in st_rc_rx_interrupt()
108 status = readl(dev->rx_base + IRB_RX_STATUS); in st_rc_rx_interrupt()
112 int_status = readl(dev->rx_base + IRB_RX_INT_STATUS); in st_rc_rx_interrupt()
115 ir_raw_event_overflow(dev->rdev); in st_rc_rx_interrupt()
116 dev_info(dev->dev, "IR RX overrun\n"); in st_rc_rx_interrupt()
118 dev->rx_base + IRB_RX_INT_CLEAR); in st_rc_rx_interrupt()
122 symbol = readl(dev->rx_base + IRB_RX_SYS); in st_rc_rx_interrupt()
123 mark = readl(dev->rx_base + IRB_RX_ON); in st_rc_rx_interrupt()
130 symbol -= mark; in st_rc_rx_interrupt()
131 if (dev->overclocking) { /* adjustments to timings */ in st_rc_rx_interrupt()
132 symbol *= dev->sample_mult; in st_rc_rx_interrupt()
133 symbol /= dev->sample_div; in st_rc_rx_interrupt()
134 mark *= dev->sample_mult; in st_rc_rx_interrupt()
135 mark /= dev->sample_div; in st_rc_rx_interrupt()
140 ir_raw_event_store(dev->rdev, &ev); in st_rc_rx_interrupt()
145 ir_raw_event_store(dev->rdev, &ev); in st_rc_rx_interrupt()
147 st_rc_send_lirc_timeout(dev->rdev); in st_rc_rx_interrupt()
152 } while (time_is_after_jiffies(timeout)); in st_rc_rx_interrupt()
154 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); in st_rc_rx_interrupt()
157 ir_raw_event_handle(dev->rdev); in st_rc_rx_interrupt()
169 reset_control_deassert(dev->rstc); in st_rc_hardware_init()
171 ret = clk_prepare_enable(dev->sys_clock); in st_rc_hardware_init()
173 dev_err(dev->dev, "Failed to prepare/enable system clock\n"); in st_rc_hardware_init()
177 baseclock = clk_get_rate(dev->sys_clock); in st_rc_hardware_init()
180 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); in st_rc_hardware_init()
183 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); in st_rc_hardware_init()
185 freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ); in st_rc_hardware_init()
187 dev->overclocking = true; in st_rc_hardware_init()
188 dev->sample_mult = 1000; in st_rc_hardware_init()
189 dev->sample_div = baseclock / (10000 * rx_sampling_freq_div); in st_rc_hardware_init()
190 rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div; in st_rc_hardware_init()
193 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); in st_rc_hardware_init()
202 dev_pm_clear_wake_irq(&pdev->dev); in st_rc_remove()
203 device_init_wakeup(&pdev->dev, false); in st_rc_remove()
204 clk_disable_unprepare(rc_dev->sys_clock); in st_rc_remove()
205 rc_unregister_device(rc_dev->rdev); in st_rc_remove()
210 struct st_rc_device *dev = rdev->priv; in st_rc_open()
214 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); in st_rc_open()
215 writel(0x01, dev->rx_base + IRB_RX_EN); in st_rc_open()
223 struct st_rc_device *dev = rdev->priv; in st_rc_close()
225 writel(0x00, dev->rx_base + IRB_RX_EN); in st_rc_close()
226 writel(0x00, dev->rx_base + IRB_RX_INT_EN); in st_rc_close()
231 int ret = -EINVAL; in st_rc_probe()
233 struct device *dev = &pdev->dev; in st_rc_probe()
235 struct device_node *np = pdev->dev.of_node; in st_rc_probe()
241 return -ENOMEM; in st_rc_probe()
246 return -ENOMEM; in st_rc_probe()
248 if (np && !of_property_read_string(np, "rx-mode", &rx_mode)) { in st_rc_probe()
251 rc_dev->rxuhfmode = true; in st_rc_probe()
253 rc_dev->rxuhfmode = false; in st_rc_probe()
255 dev_err(dev, "Unsupported rx mode [%s]\n", rx_mode); in st_rc_probe()
263 rc_dev->sys_clock = devm_clk_get(dev, NULL); in st_rc_probe()
264 if (IS_ERR(rc_dev->sys_clock)) { in st_rc_probe()
266 ret = PTR_ERR(rc_dev->sys_clock); in st_rc_probe()
270 rc_dev->irq = platform_get_irq(pdev, 0); in st_rc_probe()
271 if (rc_dev->irq < 0) { in st_rc_probe()
272 ret = rc_dev->irq; in st_rc_probe()
276 rc_dev->base = devm_platform_ioremap_resource(pdev, 0); in st_rc_probe()
277 if (IS_ERR(rc_dev->base)) { in st_rc_probe()
278 ret = PTR_ERR(rc_dev->base); in st_rc_probe()
282 if (rc_dev->rxuhfmode) in st_rc_probe()
283 rc_dev->rx_base = rc_dev->base + 0x40; in st_rc_probe()
285 rc_dev->rx_base = rc_dev->base; in st_rc_probe()
287 rc_dev->rstc = reset_control_get_optional_exclusive(dev, NULL); in st_rc_probe()
288 if (IS_ERR(rc_dev->rstc)) { in st_rc_probe()
289 ret = PTR_ERR(rc_dev->rstc); in st_rc_probe()
293 rc_dev->dev = dev; in st_rc_probe()
299 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; in st_rc_probe()
300 /* rx sampling rate is 10Mhz */ in st_rc_probe()
301 rdev->rx_resolution = 100; in st_rc_probe()
302 rdev->timeout = MAX_SYMB_TIME; in st_rc_probe()
303 rdev->priv = rc_dev; in st_rc_probe()
304 rdev->open = st_rc_open; in st_rc_probe()
305 rdev->close = st_rc_close; in st_rc_probe()
306 rdev->driver_name = IR_ST_NAME; in st_rc_probe()
307 rdev->map_name = RC_MAP_EMPTY; in st_rc_probe()
308 rdev->device_name = "ST Remote Control Receiver"; in st_rc_probe()
314 rc_dev->rdev = rdev; in st_rc_probe()
315 if (devm_request_irq(dev, rc_dev->irq, st_rc_rx_interrupt, in st_rc_probe()
317 dev_err(dev, "IRQ %d register failed\n", rc_dev->irq); in st_rc_probe()
318 ret = -EINVAL; in st_rc_probe()
324 dev_pm_set_wake_irq(dev, rc_dev->irq); in st_rc_probe()
332 dev_info(dev, "setup in %s mode\n", rc_dev->rxuhfmode ? "UHF" : "IR"); in st_rc_probe()
339 clk_disable_unprepare(rc_dev->sys_clock); in st_rc_probe()
352 if (!enable_irq_wake(rc_dev->irq)) in st_rc_suspend()
353 rc_dev->irq_wake = 1; in st_rc_suspend()
355 return -EINVAL; in st_rc_suspend()
358 writel(0x00, rc_dev->rx_base + IRB_RX_EN); in st_rc_suspend()
359 writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN); in st_rc_suspend()
360 clk_disable_unprepare(rc_dev->sys_clock); in st_rc_suspend()
361 reset_control_assert(rc_dev->rstc); in st_rc_suspend()
371 struct rc_dev *rdev = rc_dev->rdev; in st_rc_resume()
373 if (rc_dev->irq_wake) { in st_rc_resume()
374 disable_irq_wake(rc_dev->irq); in st_rc_resume()
375 rc_dev->irq_wake = 0; in st_rc_resume()
382 if (rdev->users) { in st_rc_resume()
383 writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN); in st_rc_resume()
384 writel(0x01, rc_dev->rx_base + IRB_RX_EN); in st_rc_resume()
397 { .compatible = "st,comms-irb", },