Lines Matching +full:0 +full:xfd00
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
19 #define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
23 #define ENE_FW1 0xF8F8 /* flagr */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
25 #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
28 #define ENE_FW1_LED_ON 0x10 /* turn on a led */
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
35 #define ENE_FW2 0xF8F9 /* flagw */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
39 #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
40 #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
43 #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
46 #define ENE_FW_RX_POINTER 0xF8FA
49 #define ENE_FW_SMPL_BUF_FAN 0xF8FB
50 #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
51 #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
55 #define ENE_GPIOFS1 0xFC01
56 #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
57 #define ENE_GPIOFS8 0xFC08
58 #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
61 #define ENEB_IRQ 0xFD09 /* IRQ number */
62 #define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
63 #define ENEB_IRQ_STATUS 0xFD80 /* irq status */
64 #define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
67 #define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
68 #define ENE_FAN_AS_IN1_EN 0xCD
69 #define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
70 #define ENE_FAN_AS_IN2_EN 0x03
73 #define ENE_IRQ 0xFE9B /* new irq settings register */
74 #define ENE_IRQ_MASK 0x0F /* irq number mask */
75 #define ENE_IRQ_UNK_EN 0x10 /* always enabled */
76 #define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
79 #define ENE_CIRCFG 0xFEC0
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
81 #define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
82 #define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
83 #define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
85 #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
86 #define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
87 #define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
88 #define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
91 #define ENE_CIRCFG2 0xFEC1
92 #define ENE_CIRCFG2_RLC 0x00
93 #define ENE_CIRCFG2_RC5 0x01
94 #define ENE_CIRCFG2_RC6 0x02
95 #define ENE_CIRCFG2_NEC 0x03
96 #define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
97 #define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
98 #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
99 #define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
102 #define ENE_CIRPF 0xFEC2
103 #define ENE_CIRHIGH 0xFEC3
104 #define ENE_CIRBIT 0xFEC4
105 #define ENE_CIRSTART 0xFEC5
106 #define ENE_CIRSTART2 0xFEC6
109 #define ENE_CIRDAT_IN 0xFEC7
113 #define ENE_CIRRLC_CFG 0xFEC8
114 #define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
118 #define ENE_CIRRLC_OUT0 0xFEC9
119 #define ENE_CIRRLC_OUT1 0xFECA
120 #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
121 #define ENE_CIRRLC_OUT_MASK 0x7F
128 #define ENE_CIRCAR_PULS 0xFECB
131 #define ENE_CIRCAR_PRD 0xFECC
132 #define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
135 #define ENE_CIRCAR_HPRD 0xFECD
138 #define ENE_CIRMOD_PRD 0xFECE
139 #define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
141 #define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
142 #define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
145 #define ENE_CIRMOD_HPRD 0xFECF
148 #define ENE_ECHV 0xFF00 /* hardware revision */
149 #define ENE_PLLFRH 0xFF16
150 #define ENE_PLLFRL 0xFF17
153 #define ENE_ECSTS 0xFF1D
154 #define ENE_ECSTS_RSRVD 0x04
156 #define ENE_ECVER_MAJOR 0xFF1E /* chip version */
157 #define ENE_ECVER_MINOR 0xFF1F
158 #define ENE_HW_VER_OLD 0xFD00
175 } while (0)