Lines Matching refs:G2_SWREG
13 #define G2_SWREG(nr) ((nr) * 4) macro
17 .base = G2_SWREG(b), \
22 #define G2_REG_VERSION G2_SWREG(0)
24 #define G2_REG_INTERRUPT G2_SWREG(1)
297 #define G2_REG_CONFIG G2_SWREG(58)
301 #define G2_OUT_LUMA_ADDR (G2_SWREG(65))
302 #define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8))
303 #define G2_VP9_SEGMENT_WRITE_ADDR (G2_SWREG(79))
304 #define G2_VP9_SEGMENT_READ_ADDR (G2_SWREG(81))
305 #define G2_OUT_CHROMA_ADDR (G2_SWREG(99))
306 #define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8))
307 #define G2_OUT_MV_ADDR (G2_SWREG(133))
308 #define G2_REF_MV_ADDR(i) (G2_SWREG(135) + ((i) * 0x8))
309 #define G2_TILE_SIZES_ADDR (G2_SWREG(167))
310 #define G2_STREAM_ADDR (G2_SWREG(169))
311 #define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171))
312 #define G2_VP9_CTX_COUNT_ADDR (G2_SWREG(171))
313 #define G2_VP9_PROBS_ADDR (G2_SWREG(173))
314 #define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175))
315 #define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177))
316 #define G2_TILE_FILTER_ADDR (G2_SWREG(179))
317 #define G2_TILE_SAO_ADDR (G2_SWREG(181))
318 #define G2_TILE_BSD_ADDR (G2_SWREG(183))
319 #define G2_DS_DST (G2_SWREG(186))
320 #define G2_DS_DST_CHR (G2_SWREG(188))
321 #define G2_OUT_COMP_LUMA_ADDR (G2_SWREG(190))
322 #define G2_REF_COMP_LUMA_ADDR(i) (G2_SWREG(192) + ((i) * 0x8))
323 #define G2_OUT_COMP_CHROMA_ADDR (G2_SWREG(224))
324 #define G2_REF_COMP_CHROMA_ADDR(i) (G2_SWREG(226) + ((i) * 0x8))