18 #define     G1_REG_INTERRUPT_DEC_SLICE_INT		BIT(17)
35 #define     G1_REG_CONFIG_TILED_MODE_MSB		BIT(17)
36 #define     G1_REG_CONFIG_DEC_OUT_TILED_E		BIT(17)
58 #define     G1_REG_DEC_CTRL0_SORENSON_E			BIT(17)
97 #define     G1_REG_DEC_CTRL2_TRANSDCTAB			BIT(17)
121 #define     G1_REG_DEC_CTRL2_HUFFMAN_E			BIT(17)
175 #define     G1_REG_DEC_CTRL5_REFPIC_MK_LEN(x)		(((x) & 0x7ff) << 17)
313 #define     G1_REG_PP_AXI_RD_ID(v)	(((v) << 24) & GENMASK(31, 24))  argument
314 #define     G1_REG_PP_AXI_WR_ID(v)	(((v) << 16) & GENMASK(23, 16))  argument
315 #define     G1_REG_PP_INSWAP32_E(v)	((v) ? BIT(10) : 0)  argument
316 #define     G1_REG_PP_DATA_DISC_E(v)	((v) ? BIT(9) : 0)  argument
317 #define     G1_REG_PP_CLK_GATE_E(v)	((v) ? BIT(8) : 0)  argument
318 #define     G1_REG_PP_IN_ENDIAN(v)	((v) ? BIT(7) : 0)  argument
319 #define     G1_REG_PP_OUT_ENDIAN(v)	((v) ? BIT(6) : 0)  argument
320 #define     G1_REG_PP_OUTSWAP32_E(v)	((v) ? BIT(5) : 0)  argument
321 #define     G1_REG_PP_MAX_BURST(v)	(((v) << 0) & GENMASK(4, 0))  argument
332 #define    G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))  argument
333 #define    G1_REG_PP_INPUT_SIZE_WIDTH(v)  (((v) << 0) & GENMASK(8, 0))  argument
335 #define     G1_REG_PP_PADD_R(v)	(((v) << 23) & GENMASK(27, 23))  argument
336 #define     G1_REG_PP_PADD_G(v)	(((v) << 18) & GENMASK(22, 18))  argument
337 #define     G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0)  argument
338 #define     G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0)  argument
339 #define     G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0)  argument
340 #define     G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0)  argument
342 #define     G1_REG_PP_PADD_B(v)	(((v) << 18) & GENMASK(22, 18))  argument
347 #define     G1_REG_PP_CONTROL_IN_FMT(v)	(((v) << 29) & GENMASK(31, 29))  argument
348 #define     G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))  argument
349 #define     G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))  argument
350 #define     G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))  argument
352 #define     G1_REG_PP_ORIG_WIDTH(v)	(((v) << 23) & GENMASK(31, 23))  argument