Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
67 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
68 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
69 #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2)
70 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1)
71 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
76 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
77 #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1)
80 #define ISPCCP2_CTRL_IF_EN BIT(0)
81 #define ISPCCP2_CTRL_PHY_SEL BIT(1)
86 #define ISPCCP2_CTRL_IO_OUT_SEL BIT(2)
89 #define ISPCCP2_CTRL_MODE BIT(4)
90 #define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9)
91 #define ISPCCP2_CTRL_INV BIT(10)
94 #define ISPCCP2_CTRL_VP_ONLY_EN BIT(11)
95 #define ISPCCP2_CTRL_VP_CLK_POL BIT(12)
105 #define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0)
106 #define ISPCCP2_LCx_CTRL_CRC_EN BIT(19)
110 #define ISPCCP2_LCx_CTRL_REGION_EN BIT(1)
125 #define ISPCCP2_LCx_DAT_SHIFT 16
130 #define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0)
131 #define ISPCCP2_LCM_CTRL_DST_PORT BIT(2)
137 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT 16
141 #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22)
142 #define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23)
146 #define ISPCCP2_LCM_VSIZE_SHIFT 16
148 #define ISPCCP2_LCM_HSIZE_SHIFT 16
204 #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16)
205 #define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17)
206 #define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18)
207 #define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19)
208 #define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20)
209 #define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21)
210 #define ISPSBL_PCR_PRV_WBL_OVF BIT(22)
211 #define ISPSBL_PCR_CCDC_WBL_OVF BIT(23)
212 #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24)
213 #define ISPSBL_PCR_CSIA_WBL_OVF BIT(25)
214 #define ISPSBL_PCR_CSIB_WBL_OVF BIT(26)
216 #define ISPSBL_CCDC_WR_0_DATA_READY BIT(21)
369 #define ISPPRV_PCR_BUSY BIT(1)
370 #define ISPPRV_PCR_SOURCE BIT(2)
371 #define ISPPRV_PCR_ONESHOT BIT(3)
372 #define ISPPRV_PCR_WIDTH BIT(4)
373 #define ISPPRV_PCR_INVALAW BIT(5)
374 #define ISPPRV_PCR_DRKFEN BIT(6)
375 #define ISPPRV_PCR_DRKFCAP BIT(7)
376 #define ISPPRV_PCR_HMEDEN BIT(8)
377 #define ISPPRV_PCR_NFEN BIT(9)
378 #define ISPPRV_PCR_CFAEN BIT(10)
387 #define ISPPRV_PCR_YNENHEN BIT(15)
388 #define ISPPRV_PCR_SUPEN BIT(16)
394 #define ISPPRV_PCR_RSZPORT BIT(19)
395 #define ISPPRV_PCR_SDRPORT BIT(20)
396 #define ISPPRV_PCR_SCOMP_EN BIT(21)
399 #define ISPPRV_PCR_GAMMA_BYPASS BIT(26)
400 #define ISPPRV_PCR_DCOREN BIT(27)
401 #define ISPPRV_PCR_DCCOUP BIT(28)
402 #define ISPPRV_PCR_DRK_FAIL BIT(31)
406 #define ISPPRV_HORZ_INFO_SPH_SHIFT 16
411 #define ISPPRV_VERT_INFO_SLV_SHIFT 16
426 #define ISPPRV_HMED_EVENDIST BIT(8)
427 #define ISPPRV_HMED_ODDDIST BIT(9)
431 #define ISPPRV_WBGAIN_COEF2_SHIFT 16
447 #define ISPPRV_WBSEL_N2_0_SHIFT 16
461 #define ISPPRV_BLKADJOFF_R_SHIFT 16
464 #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16
467 #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16
470 #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16
473 #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16
478 #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16
496 #define ISPPRV_CSC_OFFSET_Y_SHIFT 16
508 #define ISPPRV_CSUP_HPYF_SHIFT 16
512 #define ISPPRV_SETUP_YC_MINY_SHIFT 16
517 /* Define bit fields within selected registers */
520 #define ISP_SYSCONFIG_AUTOIDLE BIT(0)
521 #define ISP_SYSCONFIG_SOFTRESET BIT(1)
529 #define IRQ0ENABLE_CSIA_IRQ BIT(0)
530 #define IRQ0ENABLE_CSIC_IRQ BIT(1)
531 #define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3)
532 #define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4)
533 #define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5)
534 #define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6)
535 #define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7)
542 #define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8)
543 #define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9)
544 #define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10)
545 #define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11)
546 #define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12)
547 #define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13)
548 #define IRQ0ENABLE_HIST_DONE_IRQ BIT(16)
549 #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17)
550 #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18)
551 #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19)
552 #define IRQ0ENABLE_PRV_DONE_IRQ BIT(20)
553 #define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24)
554 #define IRQ0ENABLE_OVF_IRQ BIT(25)
555 #define IRQ0ENABLE_PING_IRQ BIT(26)
556 #define IRQ0ENABLE_PONG_IRQ BIT(27)
557 #define IRQ0ENABLE_MMU_ERR_IRQ BIT(28)
558 #define IRQ0ENABLE_OCP_ERR_IRQ BIT(29)
559 #define IRQ0ENABLE_SEC_ERR_IRQ BIT(30)
560 #define IRQ0ENABLE_HS_VS_IRQ BIT(31)
562 #define IRQ0STATUS_CSIA_IRQ BIT(0)
563 #define IRQ0STATUS_CSI2C_IRQ BIT(1)
564 #define IRQ0STATUS_CCP2_LCM_IRQ BIT(3)
565 #define IRQ0STATUS_CCP2_LC0_IRQ BIT(4)
569 #define IRQ0STATUS_CSIB_LC1_IRQ BIT(5)
570 #define IRQ0STATUS_CSIB_LC2_IRQ BIT(6)
571 #define IRQ0STATUS_CSIB_LC3_IRQ BIT(7)
572 #define IRQ0STATUS_CCDC_VD0_IRQ BIT(8)
573 #define IRQ0STATUS_CCDC_VD1_IRQ BIT(9)
574 #define IRQ0STATUS_CCDC_VD2_IRQ BIT(10)
575 #define IRQ0STATUS_CCDC_ERR_IRQ BIT(11)
576 #define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12)
577 #define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13)
578 #define IRQ0STATUS_HIST_DONE_IRQ BIT(16)
579 #define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17)
580 #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18)
581 #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19)
582 #define IRQ0STATUS_PRV_DONE_IRQ BIT(20)
583 #define IRQ0STATUS_RSZ_DONE_IRQ BIT(24)
584 #define IRQ0STATUS_OVF_IRQ BIT(25)
585 #define IRQ0STATUS_PING_IRQ BIT(26)
586 #define IRQ0STATUS_PONG_IRQ BIT(27)
587 #define IRQ0STATUS_MMU_ERR_IRQ BIT(28)
588 #define IRQ0STATUS_OCP_ERR_IRQ BIT(29)
589 #define IRQ0STATUS_SEC_ERR_IRQ BIT(30)
590 #define IRQ0STATUS_HS_VS_IRQ BIT(31)
610 #define ISPCTRL_PAR_CLK_POL_INV BIT(4)
611 #define ISPCTRL_PING_PONG_EN BIT(5)
618 #define ISPCTRL_CCDC_CLK_EN BIT(8)
619 #define ISPCTRL_SCMP_CLK_EN BIT(9)
620 #define ISPCTRL_H3A_CLK_EN BIT(10)
621 #define ISPCTRL_HIST_CLK_EN BIT(11)
622 #define ISPCTRL_PREV_CLK_EN BIT(12)
623 #define ISPCTRL_RSZ_CLK_EN BIT(13)
631 #define ISPCTRL_CCDC_RAM_EN BIT(16)
632 #define ISPCTRL_PREV_RAM_EN BIT(17)
633 #define ISPCTRL_SBL_RD_RAM_EN BIT(18)
634 #define ISPCTRL_SBL_WR1_RAM_EN BIT(19)
635 #define ISPCTRL_SBL_WR0_RAM_EN BIT(20)
636 #define ISPCTRL_SBL_AUTOIDLE BIT(21)
637 #define ISPCTRL_SBL_SHARED_WPORTC BIT(26)
638 #define ISPCTRL_SBL_SHARED_RPORTA BIT(27)
639 #define ISPCTRL_SBL_SHARED_RPORTB BIT(28)
640 #define ISPCTRL_JPEG_FLUSH BIT(30)
641 #define ISPCTRL_CCDC_FLUSH BIT(31)
658 #define ISPTCTRL_CTRL_SHUTEN BIT(21)
659 #define ISPTCTRL_CTRL_PSTRBEN BIT(22)
660 #define ISPTCTRL_CTRL_STRBEN BIT(23)
661 #define ISPTCTRL_CTRL_SHUTPOL BIT(24)
662 #define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26)
669 #define ISPTCTRL_CTRL_GRESETEn BIT(29)
670 #define ISPTCTRL_CTRL_GRESETPOL BIT(30)
671 #define ISPTCTRL_CTRL_GRESETDIR BIT(31)
679 #define ISPCCDC_PID_TID_SHIFT 16
682 #define ISPCCDC_PCR_BUSY BIT(1)
685 #define ISPCCDC_SYN_MODE_FLDOUT BIT(1)
686 #define ISPCCDC_SYN_MODE_VDPOL BIT(2)
687 #define ISPCCDC_SYN_MODE_HDPOL BIT(3)
688 #define ISPCCDC_SYN_MODE_FLDPOL BIT(4)
689 #define ISPCCDC_SYN_MODE_EXWEN BIT(5)
690 #define ISPCCDC_SYN_MODE_DATAPOL BIT(6)
691 #define ISPCCDC_SYN_MODE_FLDMODE BIT(7)
698 #define ISPCCDC_SYN_MODE_PACK8 BIT(11)
703 #define ISPCCDC_SYN_MODE_LPF BIT(14)
704 #define ISPCCDC_SYN_MODE_FLDSTAT BIT(15)
705 #define ISPCCDC_SYN_MODE_VDHDEN BIT(16)
706 #define ISPCCDC_SYN_MODE_WEN BIT(17)
707 #define ISPCCDC_SYN_MODE_VP2SDR BIT(18)
708 #define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19)
711 #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
714 #define ISPCCDC_PIX_LINES_PPLN_SHIFT 16
718 #define ISPCCDC_HORZ_INFO_SPH_SHIFT 16
722 #define ISPCCDC_VERT_START_SLV0_SHIFT 16
729 #define ISPCCDC_CULLING_CULHODD_SHIFT 16
734 #define ISPCCDC_SDOFST_FIINV BIT(14)
746 #define ISPCCDC_CLAMP_CLAMPEN BIT(31)
760 #define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16
771 #define ISPCCDC_BLKCMP_GR_CY_SHIFT 16
775 #define ISPCCDC_FPC_FPCEN BIT(15)
776 #define ISPCCDC_FPC_FPERR BIT(16)
780 #define ISPCCDC_VDINT_0_SHIFT 16
787 #define ISPCCDC_ALAW_CCDTBL BIT(3)
790 #define ISPCCDC_REC656IF_ECCFVH BIT(1)
792 #define ISPCCDC_CFG_BW656 BIT(5)
794 #define ISPCCDC_CFG_WENLOG BIT(8)
797 #define ISPCCDC_CFG_Y8POS BIT(11)
798 #define ISPCCDC_CFG_BSWD BIT(12)
799 #define ISPCCDC_CFG_MSBINVI BIT(13)
800 #define ISPCCDC_CFG_VDLC BIT(15)
803 #define ISPCCDC_FMTCFG_LNALT BIT(1)
812 #define ISPCCDC_FMTCFG_VPEN BIT(15)
815 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
816 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
817 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
818 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
819 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
820 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
823 #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16
826 #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16
840 #define ISPRSZ_PID_TID_SHIFT 16
842 #define ISPRSZ_PCR_ENABLE BIT(0)
843 #define ISPRSZ_PCR_BUSY BIT(1)
844 #define ISPRSZ_PCR_ONESHOT BIT(2)
856 #define ISPRSZ_CNT_YCPOS BIT(26)
857 #define ISPRSZ_CNT_INPTYP BIT(27)
858 #define ISPRSZ_CNT_INPSRC BIT(28)
859 #define ISPRSZ_CNT_CBILIN BIT(29)
864 #define ISPRSZ_OUT_SIZE_VERT_SHIFT 16
871 #define ISPRSZ_IN_START_VERT_ST_SHIFT 16
878 #define ISPRSZ_IN_SIZE_VERT_SHIFT 16
900 #define ISPRSZ_HFILT_COEF1_SHIFT 16
906 #define ISPRSZ_HFILT32_COEF3_SHIFT 16
911 #define ISPRSZ_HFILT54_COEF5_SHIFT 16
916 #define ISPRSZ_HFILT76_COEFF7_SHIFT 16
921 #define ISPRSZ_HFILT98_COEFF9_SHIFT 16
926 #define ISPRSZ_HFILT1110_COEF11_SHIFT 16
931 #define ISPRSZ_HFILT1312_COEFF13_SHIFT 16
936 #define ISPRSZ_HFILT1514_COEFF15_SHIFT 16
941 #define ISPRSZ_HFILT1716_COEF17_SHIFT 16
946 #define ISPRSZ_HFILT1918_COEF19_SHIFT 16
951 #define ISPRSZ_HFILT2120_COEF21_SHIFT 16
956 #define ISPRSZ_HFILT2322_COEF23_SHIFT 16
961 #define ISPRSZ_HFILT2524_COEF25_SHIFT 16
966 #define ISPRSZ_HFILT2726_COEF27_SHIFT 16
971 #define ISPRSZ_HFILT2928_COEF29_SHIFT 16
976 #define ISPRSZ_HFILT3130_COEF31_SHIFT 16
982 #define ISPRSZ_VFILT_COEF1_SHIFT 16
988 #define ISPRSZ_VFILT10_COEF1_SHIFT 16
993 #define ISPRSZ_VFILT32_COEF3_SHIFT 16
998 #define ISPRSZ_VFILT54_COEF5_SHIFT 16
1003 #define ISPRSZ_VFILT76_COEFF7_SHIFT 16
1008 #define ISPRSZ_VFILT98_COEFF9_SHIFT 16
1013 #define ISPRSZ_VFILT1110_COEF11_SHIFT 16
1018 #define ISPRSZ_VFILT1312_COEFF13_SHIFT 16
1023 #define ISPRSZ_VFILT1514_COEFF15_SHIFT 16
1028 #define ISPRSZ_VFILT1716_COEF17_SHIFT 16
1033 #define ISPRSZ_VFILT1918_COEF19_SHIFT 16
1038 #define ISPRSZ_VFILT2120_COEF21_SHIFT 16
1043 #define ISPRSZ_VFILT2322_COEF23_SHIFT 16
1048 #define ISPRSZ_VFILT2524_COEF25_SHIFT 16
1053 #define ISPRSZ_VFILT2726_COEF27_SHIFT 16
1058 #define ISPRSZ_VFILT2928_COEF29_SHIFT 16
1063 #define ISPRSZ_VFILT3130_COEF31_SHIFT 16
1075 #define ISPRSZ_YENH_ALGO_SHIFT 16
1084 #define ISPH3A_PCR_BUSYAF BIT(15)
1085 #define ISPH3A_PCR_BUSYAEAWB BIT(18)
1098 #define ISPH3A_AEWINSTART_WINSV_SHIFT 16
1103 #define ISPH3A_AEWINBLK_WINSV_SHIFT 16
1132 #define ISPHIST_WB_GAIN_WG01_SHIFT 16
1140 #define ISPHIST_REG_START_SHIFT 16
1162 #define ISPHIST_HV_INFO_HSIZE_SHIFT 16
1169 #define ISPCCDC_LSC_ENABLE BIT(0)
1170 #define ISPCCDC_LSC_BUSY BIT(7)
1177 #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6)
1182 #define ISPCCDC_LSC_INITIAL_Y_SHIFT 16
1184 /* -----------------------------------------------------------------------------
1199 #define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1)
1200 #define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0)
1203 #define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0)
1206 #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14)
1207 #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13)
1208 #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12)
1209 #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11)
1210 #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10)
1211 #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9)
1212 #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8)
1213 #define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n)
1217 #define ISPCSI2_CTRL_VP_CLK_EN BIT(15)
1218 #define ISPCSI2_CTRL_VP_ONLY_EN BIT(11)
1222 #define ISPCSI2_CTRL_DBG_EN BIT(7)
1226 #define ISPCSI2_CTRL_FRAME BIT(3)
1227 #define ISPCSI2_CTRL_ECC_EN BIT(2)
1228 #define ISPCSI2_CTRL_SECURE BIT(1)
1229 #define ISPCSI2_CTRL_IF_EN BIT(0)
1234 #define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30)
1235 #define ISPCSI2_PHY_CFG_RESET_DONE BIT(29)
1254 #define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24)
1303 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26)
1304 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25)
1305 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24)
1306 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23)
1307 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22)
1308 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21)
1309 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20)
1310 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19)
1311 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18)
1312 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17)
1313 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16)
1314 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15)
1315 #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14)
1316 #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13)
1317 #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12)
1318 #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11)
1319 #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10)
1320 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9)
1321 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8)
1322 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7)
1323 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6)
1324 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5)
1325 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4)
1326 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3)
1327 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2)
1328 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1)
1329 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0)
1333 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26)
1334 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25)
1335 #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24)
1336 #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23)
1337 #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22)
1338 #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21)
1339 #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20)
1340 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19)
1341 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18)
1342 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17)
1343 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16)
1344 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15)
1345 #define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14)
1346 #define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13)
1347 #define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12)
1348 #define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11)
1349 #define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10)
1350 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9)
1351 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8)
1352 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7)
1353 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6)
1354 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5)
1355 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4)
1356 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3)
1357 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2)
1358 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1)
1359 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0)
1363 #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) (1 << ((16 * ((n) - 1)) + 15))
1364 #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) (1 << ((16 * ((n) - 1)) + 14))
1365 #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) (1 << ((16 * ((n) - 1)) + 13))
1366 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1))
1374 #define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7)
1375 #define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6)
1376 #define ISPCSI2_CTX_CTRL1_CS_EN BIT(5)
1377 #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4)
1378 #define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3)
1379 #define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0)
1388 #define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10)
1392 #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT 16
1404 #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8)
1405 #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7)
1406 #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6)
1407 #define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5)
1408 #define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3)
1409 #define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2)
1410 #define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1)
1411 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0)
1414 #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8)
1415 #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7)
1416 #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6)
1417 #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5)
1418 #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3)
1419 #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2)
1420 #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1)
1421 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0)
1430 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT 16
1437 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT 16
1444 /* -----------------------------------------------------------------------------
1457 #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29)
1459 #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25)
1496 /* -----------------------------------------------------------------------------
1497 * CONTROL registers for CSI-2 phy routing
1501 #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7)
1502 #define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8)
1503 #define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10)
1504 #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12)
1505 #define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13)
1516 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4)