Lines Matching +full:0 +full:x030
21 #define ISP_REVISION (0x000)
22 #define ISP_SYSCONFIG (0x004)
23 #define ISP_SYSSTATUS (0x008)
24 #define ISP_IRQ0ENABLE (0x00C)
25 #define ISP_IRQ0STATUS (0x010)
26 #define ISP_IRQ1ENABLE (0x014)
27 #define ISP_IRQ1STATUS (0x018)
28 #define ISP_TCTRL_GRESET_LENGTH (0x030)
29 #define ISP_TCTRL_PSTRB_REPLAY (0x034)
30 #define ISP_CTRL (0x040)
31 #define ISP_SECURE (0x044)
32 #define ISP_TCTRL_CTRL (0x050)
33 #define ISP_TCTRL_FRAME (0x054)
34 #define ISP_TCTRL_PSTRB_DELAY (0x058)
35 #define ISP_TCTRL_STRB_DELAY (0x05C)
36 #define ISP_TCTRL_SHUT_DELAY (0x060)
37 #define ISP_TCTRL_PSTRB_LENGTH (0x064)
38 #define ISP_TCTRL_STRB_LENGTH (0x068)
39 #define ISP_TCTRL_SHUT_LENGTH (0x06C)
40 #define ISP_PING_PONG_ADDR (0x070)
41 #define ISP_PING_PONG_MEM_RANGE (0x074)
42 #define ISP_PING_PONG_BUF_SIZE (0x078)
46 #define ISPCCP2_REVISION (0x000)
47 #define ISPCCP2_SYSCONFIG (0x004)
49 #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
52 (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
54 (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
56 (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
57 #define ISPCCP2_SYSSTATUS (0x008)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
59 #define ISPCCP2_LC01_IRQENABLE (0x00C)
60 #define ISPCCP2_LC01_IRQSTATUS (0x010)
71 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
73 #define ISPCCP2_LC23_IRQENABLE (0x014)
74 #define ISPCCP2_LC23_IRQSTATUS (0x018)
75 #define ISPCCP2_LCM_IRQENABLE (0x02C)
76 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
78 #define ISPCCP2_LCM_IRQSTATUS (0x030)
79 #define ISPCCP2_CTRL (0x040)
80 #define ISPCCP2_CTRL_IF_EN BIT(0)
82 #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
84 #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
87 #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
92 #define ISPCCP2_CTRL_INV_MASK 0x1
96 #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
99 #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
101 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
102 #define ISPCCP2_DBG (0x044)
103 #define ISPCCP2_GNQ (0x048)
104 #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
105 #define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0)
107 #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
111 #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
113 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
114 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2
115 #define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f
116 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3
117 #define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x))
118 #define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x))
119 #define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
120 #define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
121 #define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
122 #define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x))
123 #define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
124 #define ISPCCP2_LCx_DAT_MASK 0xFFF
126 #define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
127 #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
128 #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
129 #define ISPCCP2_LCM_CTRL (0x1D0)
130 #define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0)
134 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
136 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7
138 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
140 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
144 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
145 #define ISPCCP2_LCM_VSIZE (0x1D4)
147 #define ISPCCP2_LCM_HSIZE (0x1D8)
149 #define ISPCCP2_LCM_PREFETCH (0x1DC)
151 #define ISPCCP2_LCM_SRC_ADDR (0x1E0)
152 #define ISPCCP2_LCM_SRC_OFST (0x1E4)
153 #define ISPCCP2_LCM_DST_ADDR (0x1E8)
154 #define ISPCCP2_LCM_DST_OFST (0x1EC)
158 #define ISPCCDC_PID (0x000)
159 #define ISPCCDC_PCR (0x004)
160 #define ISPCCDC_SYN_MODE (0x008)
161 #define ISPCCDC_HD_VD_WID (0x00C)
162 #define ISPCCDC_PIX_LINES (0x010)
163 #define ISPCCDC_HORZ_INFO (0x014)
164 #define ISPCCDC_VERT_START (0x018)
165 #define ISPCCDC_VERT_LINES (0x01C)
166 #define ISPCCDC_CULLING (0x020)
167 #define ISPCCDC_HSIZE_OFF (0x024)
168 #define ISPCCDC_SDOFST (0x028)
169 #define ISPCCDC_SDR_ADDR (0x02C)
170 #define ISPCCDC_CLAMP (0x030)
171 #define ISPCCDC_DCSUB (0x034)
172 #define ISPCCDC_COLPTN (0x038)
173 #define ISPCCDC_BLKCMP (0x03C)
174 #define ISPCCDC_FPC (0x040)
175 #define ISPCCDC_FPC_ADDR (0x044)
176 #define ISPCCDC_VDINT (0x048)
177 #define ISPCCDC_ALAW (0x04C)
178 #define ISPCCDC_REC656IF (0x050)
179 #define ISPCCDC_CFG (0x054)
180 #define ISPCCDC_FMTCFG (0x058)
181 #define ISPCCDC_FMT_HORZ (0x05C)
182 #define ISPCCDC_FMT_VERT (0x060)
183 #define ISPCCDC_FMT_ADDR0 (0x064)
184 #define ISPCCDC_FMT_ADDR1 (0x068)
185 #define ISPCCDC_FMT_ADDR2 (0x06C)
186 #define ISPCCDC_FMT_ADDR3 (0x070)
187 #define ISPCCDC_FMT_ADDR4 (0x074)
188 #define ISPCCDC_FMT_ADDR5 (0x078)
189 #define ISPCCDC_FMT_ADDR6 (0x07C)
190 #define ISPCCDC_FMT_ADDR7 (0x080)
191 #define ISPCCDC_PRGEVEN0 (0x084)
192 #define ISPCCDC_PRGEVEN1 (0x088)
193 #define ISPCCDC_PRGODD0 (0x08C)
194 #define ISPCCDC_PRGODD1 (0x090)
195 #define ISPCCDC_VP_OUT (0x094)
197 #define ISPCCDC_LSC_CONFIG (0x098)
198 #define ISPCCDC_LSC_INITIAL (0x09C)
199 #define ISPCCDC_LSC_TABLE_BASE (0x0A0)
200 #define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
203 #define ISPSBL_PCR 0x4
215 #define ISPSBL_CCDC_WR_0 (0x028)
217 #define ISPSBL_CCDC_WR_1 (0x02C)
218 #define ISPSBL_CCDC_WR_2 (0x030)
219 #define ISPSBL_CCDC_WR_3 (0x034)
221 #define ISPSBL_SDR_REQ_EXP 0xF8
222 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0
223 #define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF)
225 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
227 #define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
230 #define ISPHIST_PID (0x000)
231 #define ISPHIST_PCR (0x004)
232 #define ISPHIST_CNT (0x008)
233 #define ISPHIST_WB_GAIN (0x00C)
234 #define ISPHIST_R0_HORZ (0x010)
235 #define ISPHIST_R0_VERT (0x014)
236 #define ISPHIST_R1_HORZ (0x018)
237 #define ISPHIST_R1_VERT (0x01C)
238 #define ISPHIST_R2_HORZ (0x020)
239 #define ISPHIST_R2_VERT (0x024)
240 #define ISPHIST_R3_HORZ (0x028)
241 #define ISPHIST_R3_VERT (0x02C)
242 #define ISPHIST_ADDR (0x030)
243 #define ISPHIST_DATA (0x034)
244 #define ISPHIST_RADD (0x038)
245 #define ISPHIST_RADD_OFF (0x03C)
246 #define ISPHIST_H_V_INFO (0x040)
249 #define ISPH3A_PID (0x000)
250 #define ISPH3A_PCR (0x004)
251 #define ISPH3A_AEWWIN1 (0x04C)
252 #define ISPH3A_AEWINSTART (0x050)
253 #define ISPH3A_AEWINBLK (0x054)
254 #define ISPH3A_AEWSUBWIN (0x058)
255 #define ISPH3A_AEWBUFST (0x05C)
256 #define ISPH3A_AFPAX1 (0x008)
257 #define ISPH3A_AFPAX2 (0x00C)
258 #define ISPH3A_AFPAXSTART (0x010)
259 #define ISPH3A_AFIIRSH (0x014)
260 #define ISPH3A_AFBUFST (0x018)
261 #define ISPH3A_AFCOEF010 (0x01C)
262 #define ISPH3A_AFCOEF032 (0x020)
263 #define ISPH3A_AFCOEF054 (0x024)
264 #define ISPH3A_AFCOEF076 (0x028)
265 #define ISPH3A_AFCOEF098 (0x02C)
266 #define ISPH3A_AFCOEF0010 (0x030)
267 #define ISPH3A_AFCOEF110 (0x034)
268 #define ISPH3A_AFCOEF132 (0x038)
269 #define ISPH3A_AFCOEF154 (0x03C)
270 #define ISPH3A_AFCOEF176 (0x040)
271 #define ISPH3A_AFCOEF198 (0x044)
272 #define ISPH3A_AFCOEF1010 (0x048)
274 #define ISPPRV_PCR (0x004)
275 #define ISPPRV_HORZ_INFO (0x008)
276 #define ISPPRV_VERT_INFO (0x00C)
277 #define ISPPRV_RSDR_ADDR (0x010)
278 #define ISPPRV_RADR_OFFSET (0x014)
279 #define ISPPRV_DSDR_ADDR (0x018)
280 #define ISPPRV_DRKF_OFFSET (0x01C)
281 #define ISPPRV_WSDR_ADDR (0x020)
282 #define ISPPRV_WADD_OFFSET (0x024)
283 #define ISPPRV_AVE (0x028)
284 #define ISPPRV_HMED (0x02C)
285 #define ISPPRV_NF (0x030)
286 #define ISPPRV_WB_DGAIN (0x034)
287 #define ISPPRV_WBGAIN (0x038)
288 #define ISPPRV_WBSEL (0x03C)
289 #define ISPPRV_CFA (0x040)
290 #define ISPPRV_BLKADJOFF (0x044)
291 #define ISPPRV_RGB_MAT1 (0x048)
292 #define ISPPRV_RGB_MAT2 (0x04C)
293 #define ISPPRV_RGB_MAT3 (0x050)
294 #define ISPPRV_RGB_MAT4 (0x054)
295 #define ISPPRV_RGB_MAT5 (0x058)
296 #define ISPPRV_RGB_OFF1 (0x05C)
297 #define ISPPRV_RGB_OFF2 (0x060)
298 #define ISPPRV_CSC0 (0x064)
299 #define ISPPRV_CSC1 (0x068)
300 #define ISPPRV_CSC2 (0x06C)
301 #define ISPPRV_CSC_OFFSET (0x070)
302 #define ISPPRV_CNT_BRT (0x074)
303 #define ISPPRV_CSUP (0x078)
304 #define ISPPRV_SETUP_YC (0x07C)
305 #define ISPPRV_SET_TBL_ADDR (0x080)
306 #define ISPPRV_SET_TBL_DATA (0x084)
307 #define ISPPRV_CDC_THR0 (0x090)
308 #define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
309 #define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
310 #define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
312 #define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
313 #define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
314 #define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
315 #define ISPPRV_NF_TABLE_ADDR 0x0C00
316 #define ISPPRV_YENH_TABLE_ADDR 0x1000
317 #define ISPPRV_CFA_TABLE_ADDR 0x1400
323 #define ISPRSZ_PID (0x000)
324 #define ISPRSZ_PCR (0x004)
325 #define ISPRSZ_CNT (0x008)
326 #define ISPRSZ_OUT_SIZE (0x00C)
327 #define ISPRSZ_IN_START (0x010)
328 #define ISPRSZ_IN_SIZE (0x014)
329 #define ISPRSZ_SDR_INADD (0x018)
330 #define ISPRSZ_SDR_INOFF (0x01C)
331 #define ISPRSZ_SDR_OUTADD (0x020)
332 #define ISPRSZ_SDR_OUTOFF (0x024)
333 #define ISPRSZ_HFILT10 (0x028)
334 #define ISPRSZ_HFILT32 (0x02C)
335 #define ISPRSZ_HFILT54 (0x030)
336 #define ISPRSZ_HFILT76 (0x034)
337 #define ISPRSZ_HFILT98 (0x038)
338 #define ISPRSZ_HFILT1110 (0x03C)
339 #define ISPRSZ_HFILT1312 (0x040)
340 #define ISPRSZ_HFILT1514 (0x044)
341 #define ISPRSZ_HFILT1716 (0x048)
342 #define ISPRSZ_HFILT1918 (0x04C)
343 #define ISPRSZ_HFILT2120 (0x050)
344 #define ISPRSZ_HFILT2322 (0x054)
345 #define ISPRSZ_HFILT2524 (0x058)
346 #define ISPRSZ_HFILT2726 (0x05C)
347 #define ISPRSZ_HFILT2928 (0x060)
348 #define ISPRSZ_HFILT3130 (0x064)
349 #define ISPRSZ_VFILT10 (0x068)
350 #define ISPRSZ_VFILT32 (0x06C)
351 #define ISPRSZ_VFILT54 (0x070)
352 #define ISPRSZ_VFILT76 (0x074)
353 #define ISPRSZ_VFILT98 (0x078)
354 #define ISPRSZ_VFILT1110 (0x07C)
355 #define ISPRSZ_VFILT1312 (0x080)
356 #define ISPRSZ_VFILT1514 (0x084)
357 #define ISPRSZ_VFILT1716 (0x088)
358 #define ISPRSZ_VFILT1918 (0x08C)
359 #define ISPRSZ_VFILT2120 (0x090)
360 #define ISPRSZ_VFILT2322 (0x094)
361 #define ISPRSZ_VFILT2524 (0x098)
362 #define ISPRSZ_VFILT2726 (0x09C)
363 #define ISPRSZ_VFILT2928 (0x0A0)
364 #define ISPRSZ_VFILT3130 (0x0A4)
365 #define ISPRSZ_YENH (0x0A8)
367 #define ISP_INT_CLR 0xFF113F11
380 #define ISPPRV_PCR_CFAFMT_MASK 0x7800
381 #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
390 #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
404 #define ISPPRV_HORZ_INFO_EPH_SHIFT 0
405 #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
407 #define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
409 #define ISPPRV_VERT_INFO_ELV_SHIFT 0
410 #define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
412 #define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
415 #define ISPPRV_AVE_EVENDIST_1 0x0
416 #define ISPPRV_AVE_EVENDIST_2 0x1
417 #define ISPPRV_AVE_EVENDIST_3 0x2
418 #define ISPPRV_AVE_EVENDIST_4 0x3
420 #define ISPPRV_AVE_ODDDIST_1 0x0
421 #define ISPPRV_AVE_ODDDIST_2 0x1
422 #define ISPPRV_AVE_ODDDIST_3 0x2
423 #define ISPPRV_AVE_ODDDIST_4 0x3
425 #define ISPPRV_HMED_THRESHOLD_SHIFT 0
429 #define ISPPRV_WBGAIN_COEF0_SHIFT 0
434 #define ISPPRV_WBSEL_COEF0 0x0
435 #define ISPPRV_WBSEL_COEF1 0x1
436 #define ISPPRV_WBSEL_COEF2 0x2
437 #define ISPPRV_WBSEL_COEF3 0x3
439 #define ISPPRV_WBSEL_N0_0_SHIFT 0
456 #define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
459 #define ISPPRV_BLKADJOFF_B_SHIFT 0
463 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
466 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
469 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
472 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
475 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
477 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
480 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
482 #define ISPPRV_CSC0_RY_SHIFT 0
486 #define ISPPRV_CSC1_RCB_SHIFT 0
490 #define ISPPRV_CSC2_RCR_SHIFT 0
494 #define ISPPRV_CSC_OFFSET_CR_SHIFT 0
498 #define ISPPRV_CNT_BRT_BRT_SHIFT 0
501 #define ISPPRV_CONTRAST_MAX 0x10
502 #define ISPPRV_CONTRAST_MIN 0xFF
503 #define ISPPRV_BRIGHT_MIN 0x00
504 #define ISPPRV_BRIGHT_MAX 0xFF
506 #define ISPPRV_CSUP_CSUPG_SHIFT 0
510 #define ISPPRV_SETUP_YC_MINC_SHIFT 0
514 #define ISPPRV_YC_MAX 0xFF
515 #define ISPPRV_YC_MIN 0x0
518 #define ISP_REVISION_SHIFT 0
520 #define ISP_SYSCONFIG_AUTOIDLE BIT(0)
523 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
524 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
525 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
527 #define ISP_SYSSTATUS_RESETDONE 0
529 #define IRQ0ENABLE_CSIA_IRQ BIT(0)
562 #define IRQ0STATUS_CSIA_IRQ BIT(0)
592 #define TCTRL_GRESET_LEN 0
594 #define TCTRL_PSTRB_REPLAY_DELAY 0
597 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
598 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
599 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
600 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3
601 #define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3
604 #define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
605 #define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
606 #define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
607 #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
613 #define ISPCTRL_SHIFT_0 (0x0 << 6)
614 #define ISPCTRL_SHIFT_2 (0x1 << 6)
615 #define ISPCTRL_SHIFT_4 (0x2 << 6)
616 #define ISPCTRL_SHIFT_MASK (0x3 << 6)
625 #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
626 #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
627 #define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
628 #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
629 #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
643 #define ISPSECURE_SECUREMODE 0
645 #define ISPTCTRL_CTRL_DIV_LOW 0x0
646 #define ISPTCTRL_CTRL_DIV_HIGH 0x1
647 #define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
649 #define ISPTCTRL_CTRL_DIVA_SHIFT 0
650 #define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
653 #define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
656 #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
665 #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
666 #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
667 #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
673 #define ISPTCTRL_FRAME_SHUT_SHIFT 0
677 #define ISPCCDC_PID_PREV_SHIFT 0
684 #define ISPCCDC_SYN_MODE_VDHDOUT 0x1
692 #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
693 #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
694 #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
695 #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
696 #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
697 #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
700 #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
710 #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
713 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
716 #define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
717 #define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff
719 #define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000
721 #define ISPCCDC_VERT_START_SLV1_SHIFT 0
723 #define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000
725 #define ISPCCDC_VERT_LINES_NLV_SHIFT 0
726 #define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff
728 #define ISPCCDC_CULLING_CULV_SHIFT 0
732 #define ISPCCDC_HSIZE_OFF_SHIFT 0
737 #define ISPCCDC_SDOFST_LOFST3_SHIFT 0
742 #define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
748 #define ISPCCDC_COLPTN_R_Ye 0x0
749 #define ISPCCDC_COLPTN_Gr_Cy 0x1
750 #define ISPCCDC_COLPTN_Gb_G 0x2
751 #define ISPCCDC_COLPTN_B_Mg 0x3
752 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
769 #define ISPCCDC_BLKCMP_B_MG_SHIFT 0
774 #define ISPCCDC_FPC_FPNUM_SHIFT 0
778 #define ISPCCDC_VDINT_1_SHIFT 0
779 #define ISPCCDC_VDINT_1_MASK 0x00007fff
781 #define ISPCCDC_VDINT_0_MASK 0x7fff0000
783 #define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0)
784 #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
785 #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
786 #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
795 #define ISPCCDC_CFG_WENLOG_AND (0 << 8)
802 #define ISPCCDC_FMTCFG_FMTEN 0x1
807 #define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000
808 #define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
809 #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
810 #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
811 #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
814 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
816 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
817 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
818 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
819 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
820 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
822 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
825 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
828 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000
829 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff
831 #define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000
832 #define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff
834 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
838 #define ISPRSZ_PID_PREV_SHIFT 0
842 #define ISPRSZ_PCR_ENABLE BIT(0)
846 #define ISPRSZ_CNT_HRSZ_SHIFT 0
848 (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
851 (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
853 #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
855 #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
861 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
863 (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
866 (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
868 #define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
870 (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
873 (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
875 #define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
877 (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
880 (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
882 #define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
883 #define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
885 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
887 (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
889 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
890 #define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
893 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
895 (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
897 #define ISPRSZ_HFILT_COEF0_SHIFT 0
899 (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
902 (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
904 #define ISPRSZ_HFILT32_COEF2_SHIFT 0
905 #define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
907 #define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
909 #define ISPRSZ_HFILT54_COEF4_SHIFT 0
910 #define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
912 #define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
914 #define ISPRSZ_HFILT76_COEFF6_SHIFT 0
915 #define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
917 #define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
919 #define ISPRSZ_HFILT98_COEFF8_SHIFT 0
920 #define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
922 #define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
924 #define ISPRSZ_HFILT1110_COEF10_SHIFT 0
925 #define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
927 #define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
929 #define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
930 #define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
932 #define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
934 #define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
935 #define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
937 #define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
939 #define ISPRSZ_HFILT1716_COEF16_SHIFT 0
940 #define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
942 #define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
944 #define ISPRSZ_HFILT1918_COEF18_SHIFT 0
945 #define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
947 #define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
949 #define ISPRSZ_HFILT2120_COEF20_SHIFT 0
950 #define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
952 #define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
954 #define ISPRSZ_HFILT2322_COEF22_SHIFT 0
955 #define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
957 #define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
959 #define ISPRSZ_HFILT2524_COEF24_SHIFT 0
960 #define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
962 #define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
964 #define ISPRSZ_HFILT2726_COEF26_SHIFT 0
965 #define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
967 #define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
969 #define ISPRSZ_HFILT2928_COEF28_SHIFT 0
970 #define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
972 #define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
974 #define ISPRSZ_HFILT3130_COEF30_SHIFT 0
975 #define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
977 #define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
979 #define ISPRSZ_VFILT_COEF0_SHIFT 0
981 (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
984 (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
986 #define ISPRSZ_VFILT10_COEF0_SHIFT 0
987 #define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
989 #define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
991 #define ISPRSZ_VFILT32_COEF2_SHIFT 0
992 #define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
994 #define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
996 #define ISPRSZ_VFILT54_COEF4_SHIFT 0
997 #define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
999 #define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
1001 #define ISPRSZ_VFILT76_COEFF6_SHIFT 0
1002 #define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
1004 #define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
1006 #define ISPRSZ_VFILT98_COEFF8_SHIFT 0
1007 #define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
1009 #define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
1011 #define ISPRSZ_VFILT1110_COEF10_SHIFT 0
1012 #define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
1014 #define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
1016 #define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
1017 #define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
1019 #define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
1021 #define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
1022 #define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
1024 #define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
1026 #define ISPRSZ_VFILT1716_COEF16_SHIFT 0
1027 #define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
1029 #define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
1031 #define ISPRSZ_VFILT1918_COEF18_SHIFT 0
1032 #define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
1034 #define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
1036 #define ISPRSZ_VFILT2120_COEF20_SHIFT 0
1037 #define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
1039 #define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
1041 #define ISPRSZ_VFILT2322_COEF22_SHIFT 0
1042 #define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
1044 #define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
1046 #define ISPRSZ_VFILT2524_COEF24_SHIFT 0
1047 #define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
1049 #define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
1051 #define ISPRSZ_VFILT2726_COEF26_SHIFT 0
1052 #define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
1054 #define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
1056 #define ISPRSZ_VFILT2928_COEF28_SHIFT 0
1057 #define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
1059 #define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
1061 #define ISPRSZ_VFILT3130_COEF30_SHIFT 0
1062 #define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
1064 #define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
1066 #define ISPRSZ_YENH_CORE_SHIFT 0
1068 (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1071 (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1074 (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1077 (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1083 #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
1087 #define ISPH3A_AEWWIN1_WINHC_SHIFT 0
1088 #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
1090 #define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
1092 #define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
1094 #define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
1096 #define ISPH3A_AEWINSTART_WINSH_SHIFT 0
1097 #define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
1099 #define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
1101 #define ISPH3A_AEWINBLK_WINH_SHIFT 0
1102 #define ISPH3A_AEWINBLK_WINH_MASK 0x7F
1104 #define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
1106 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
1107 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
1109 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
1111 #define ISPHIST_PCR_ENABLE_SHIFT 0
1112 #define ISPHIST_PCR_ENABLE_MASK 0x01
1114 #define ISPHIST_PCR_BUSY 0x02
1117 #define ISPHIST_CNT_DATASIZE_MASK 0x0100
1119 #define ISPHIST_CNT_CLEAR_MASK 0x080
1122 #define ISPHIST_CNT_CFA_MASK 0x040
1124 #define ISPHIST_CNT_BINS_MASK 0x030
1126 #define ISPHIST_CNT_SOURCE_MASK 0x08
1127 #define ISPHIST_CNT_SHIFT_SHIFT 0
1128 #define ISPHIST_CNT_SHIFT_MASK 0x07
1131 #define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
1133 #define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
1135 #define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
1136 #define ISPHIST_WB_GAIN_WG03_SHIFT 0
1137 #define ISPHIST_WB_GAIN_WG03_MASK 0xFF
1139 #define ISPHIST_REG_START_END_MASK 0x3FFF
1141 #define ISPHIST_REG_END_SHIFT 0
1150 #define ISPHIST_ADDR_SHIFT 0
1151 #define ISPHIST_ADDR_MASK 0x3FF
1153 #define ISPHIST_DATA_SHIFT 0
1154 #define ISPHIST_DATA_MASK 0xFFFFF
1156 #define ISPHIST_RADD_SHIFT 0
1157 #define ISPHIST_RADD_MASK 0xFFFFFFFF
1159 #define ISPHIST_RADD_OFF_SHIFT 0
1160 #define ISPHIST_RADD_OFF_MASK 0xFFFF
1163 #define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
1164 #define ISPHIST_HV_INFO_VSIZE_SHIFT 0
1165 #define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
1167 #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
1169 #define ISPCCDC_LSC_ENABLE BIT(0)
1171 #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
1173 #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
1175 #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
1179 #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
1180 #define ISPCCDC_LSC_INITIAL_X_SHIFT 0
1181 #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
1185 * CSI2 receiver registers (ES2.0)
1188 #define ISPCSI2_REVISION (0x000)
1189 #define ISPCSI2_SYSCONFIG (0x010)
1192 (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1194 (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1196 (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1198 (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1200 #define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0)
1202 #define ISPCSI2_SYSSTATUS (0x014)
1203 #define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0)
1205 #define ISPCSI2_IRQSTATUS (0x018)
1215 #define ISPCSI2_IRQENABLE (0x01c)
1216 #define ISPCSI2_CTRL (0x040)
1229 #define ISPCSI2_CTRL_IF_EN BIT(0)
1231 #define ISPCSI2_DBG_H (0x044)
1232 #define ISPCSI2_GNQ (0x048)
1233 #define ISPCSI2_PHY_CFG (0x050)
1238 (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1240 (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1242 (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1244 (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1247 (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1249 (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1251 (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1253 (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1258 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1260 (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1262 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1266 (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1268 (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1270 (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1272 (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1274 (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1276 (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1278 (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1282 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1284 (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1286 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1288 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0
1290 (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1292 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1294 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1296 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1298 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1300 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1302 #define ISPCSI2_PHY_IRQSTATUS (0x054)
1329 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0)
1331 #define ISPCSI2_SHORT_PACKET (0x05c)
1332 #define ISPCSI2_PHY_IRQENABLE (0x060)
1359 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0)
1361 #define ISPCSI2_DBG_P (0x068)
1362 #define ISPCSI2_TIMING (0x06c)
1368 (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1370 #define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
1373 (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1379 #define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0)
1381 #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
1384 (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1387 (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1389 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
1391 (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1394 (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1396 #define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
1397 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0
1399 (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1401 #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
1402 #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
1403 #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
1411 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0)
1413 #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
1421 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0)
1423 #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
1426 (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1429 #define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n))
1432 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1433 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0
1435 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1436 #define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n))
1439 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1440 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0
1442 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1448 #define ISPCSIPHY_REG0 (0x000)
1451 (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1452 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0
1454 (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1456 #define ISPCSIPHY_REG1 (0x004)
1462 (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1465 (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1469 (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1473 (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1474 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0
1476 (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1479 #define ISPCSIPHY_REG2 (0x008)
1482 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1485 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1488 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1491 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1492 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0
1494 (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1509 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT 0
1510 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY 0x0
1511 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE 0x1
1512 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK 0x2
1513 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
1514 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3