24 #define regr(reg)               readl((reg) + vpif_base)  macro
131 	regw((regr(reg)) | (0x01 << bit), reg);  in vpif_set_bit()
136 	regw(((regr(reg)) & ~(0x01 << bit)), reg);  in vpif_clr_bit()
213 #define channel0_intr_assert()	(regw((regr(VPIF_CH0_CTRL)|\
217 #define channel1_intr_assert()	(regw((regr(VPIF_CH1_CTRL)|\
221 #define channel2_intr_assert()	(regw((regr(VPIF_CH2_CTRL)|\
225 #define channel3_intr_assert()	(regw((regr(VPIF_CH3_CTRL)|\
266 		regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);  in enable_channel0()
268 		regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);  in enable_channel0()
275 		regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);  in enable_channel1()
277 		regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);  in enable_channel1()
288 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel0_intr_enable()
289 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel0_intr_enable()
291 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);  in channel0_intr_enable()
292 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),  in channel0_intr_enable()
295 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);  in channel0_intr_enable()
296 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),  in channel0_intr_enable()
310 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel1_intr_enable()
311 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel1_intr_enable()
313 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);  in channel1_intr_enable()
314 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),  in channel1_intr_enable()
317 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);  in channel1_intr_enable()
318 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),  in channel1_intr_enable()
421 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);  in enable_channel2()
422 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);  in enable_channel2()
424 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);  in enable_channel2()
425 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);  in enable_channel2()
433 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);  in enable_channel3()
434 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);  in enable_channel3()
436 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);  in enable_channel3()
437 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);  in enable_channel3()
449 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel2_intr_enable()
450 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel2_intr_enable()
451 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);  in channel2_intr_enable()
452 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),  in channel2_intr_enable()
455 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);  in channel2_intr_enable()
456 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),  in channel2_intr_enable()
470 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel3_intr_enable()
471 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel3_intr_enable()
473 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);  in channel3_intr_enable()
474 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),  in channel3_intr_enable()
477 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);  in channel3_intr_enable()
478 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),  in channel3_intr_enable()
603 	status = regr(VPIF_STATUS) & mask;  in vpif_intr_status()