43 #define CAL_HL_IRQSTATUS_RAW(m)		(0x20U + (m) * 0x10U)  argument
44 #define CAL_HL_IRQSTATUS(m)		(0x24U + (m) * 0x10U)  argument
45 #define CAL_HL_IRQENABLE_SET(m)		(0x28U + (m) * 0x10U)  argument
46 #define CAL_HL_IRQENABLE_CLR(m)		(0x2cU + (m) * 0x10U)  argument
47 #define CAL_PIX_PROC(m)			(0xc0U + (m) * 0x4U)  argument
63 #define CAL_WR_DMA_CTRL(m)		(0x200U + (m) * 0x10U)  argument
64 #define CAL_WR_DMA_ADDR(m)		(0x204U + (m) * 0x10U)  argument
65 #define CAL_WR_DMA_OFST(m)		(0x208U + (m) * 0x10U)  argument
66 #define CAL_WR_DMA_XSIZE(m)		(0x20cU + (m) * 0x10U)  argument
67 #define CAL_CSI2_PPI_CTRL(m)		(0x300U + (m) * 0x80U)  argument
68 #define CAL_CSI2_COMPLEXIO_CFG(m)	(0x304U + (m) * 0x80U)  argument
69 #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m)	(0x308U + (m) * 0x80U)  argument
70 #define CAL_CSI2_SHORT_PACKET(m)	(0x30cU + (m) * 0x80U)  argument
71 #define CAL_CSI2_COMPLEXIO_IRQENABLE(m)	(0x310U + (m) * 0x80U)  argument
72 #define CAL_CSI2_TIMING(m)		(0x314U + (m) * 0x80U)  argument
73 #define CAL_CSI2_VC_IRQENABLE(m)	(0x318U + (m) * 0x80U)  argument
74 #define CAL_CSI2_VC_IRQSTATUS(m)	(0x328U + (m) * 0x80U)  argument
93 #define CAL_HL_REVISION_MAJOR_MASK		GENMASK(10, 8)
102 #define CAL_HL_HWINFO_PCTX_MASK			GENMASK(12, 8)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m)		BIT(m)  argument
129 #define CAL_HL_IRQ_WDMA_START_MASK(m)		BIT(m)  argument
133 #define CAL_HL_IRQ_CIO_MASK(i)			BIT(16 + (i) * 8)
134 #define CAL_HL_IRQ_VC_MASK(i)			BIT(17 + (i) * 8)
304 #define CAL_WR_DMA_CTRL_DTAG_MASK		GENMASK(8, 6)
348 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK	GENMASK(10, 8)
380 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK	BIT(8)
409 #define CAL_CSI2_VC_IRQ_FS_IRQ_MASK(n)			BIT(0 + ((n) * 8))
410 #define CAL_CSI2_VC_IRQ_FE_IRQ_MASK(n)			BIT(1 + ((n) * 8))
411 #define CAL_CSI2_VC_IRQ_LS_IRQ_MASK(n)			BIT(2 + ((n) * 8))
412 #define CAL_CSI2_VC_IRQ_LE_IRQ_MASK(n)			BIT(3 + ((n) * 8))
413 #define CAL_CSI2_VC_IRQ_CS_IRQ_MASK(n)			BIT(4 + ((n) * 8))
414 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(n)	BIT(5 + ((n) * 8))
420 #define CAL_CSI2_CTX_CPORT_MASK		GENMASK(12, 8)
432 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK		GENMASK(15, 8)
438 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK		GENMASK(9, 8)