Lines Matching +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - CAMERARX
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
28 /* ------------------------------------------------------------------
30 * ------------------------------------------------------------------
33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset) in camerarx_read() argument
35 return ioread32(phy->base + offset); in camerarx_read()
38 static inline void camerarx_write(struct cal_camerarx *phy, u32 offset, u32 val) in camerarx_write() argument
40 iowrite32(val, phy->base + offset); in camerarx_write()
43 /* ------------------------------------------------------------------
45 * ------------------------------------------------------------------
48 static s64 cal_camerarx_get_ext_link_freq(struct cal_camerarx *phy) in cal_camerarx_get_ext_link_freq() argument
50 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2 = &phy->endpoint.bus.mipi_csi2; in cal_camerarx_get_ext_link_freq()
51 u32 num_lanes = mipi_csi2->num_data_lanes; in cal_camerarx_get_ext_link_freq()
58 state = v4l2_subdev_get_locked_active_state(&phy->subdev); in cal_camerarx_get_ext_link_freq()
62 fmtinfo = cal_format_by_code(fmt->code); in cal_camerarx_get_ext_link_freq()
64 return -EINVAL; in cal_camerarx_get_ext_link_freq()
66 bpp = fmtinfo->bpp; in cal_camerarx_get_ext_link_freq()
68 freq = v4l2_get_link_freq(phy->source->ctrl_handler, bpp, 2 * num_lanes); in cal_camerarx_get_ext_link_freq()
70 phy_err(phy, "failed to get link freq for subdev '%s'\n", in cal_camerarx_get_ext_link_freq()
71 phy->source->name); in cal_camerarx_get_ext_link_freq()
75 phy_dbg(3, phy, "Source Link Freq: %llu\n", freq); in cal_camerarx_get_ext_link_freq()
80 static void cal_camerarx_lane_config(struct cal_camerarx *phy) in cal_camerarx_lane_config() argument
82 u32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)); in cal_camerarx_lane_config()
86 &phy->endpoint.bus.mipi_csi2; in cal_camerarx_lane_config()
89 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); in cal_camerarx_lane_config()
90 cal_set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask); in cal_camerarx_lane_config()
91 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) { in cal_camerarx_lane_config()
98 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); in cal_camerarx_lane_config()
99 cal_set_field(&val, mipi_csi2->lane_polarities[lane + 1], in cal_camerarx_lane_config()
103 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val); in cal_camerarx_lane_config()
104 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n", in cal_camerarx_lane_config()
105 phy->instance, val); in cal_camerarx_lane_config()
108 static void cal_camerarx_enable(struct cal_camerarx *phy) in cal_camerarx_enable() argument
110 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes; in cal_camerarx_enable()
112 regmap_field_write(phy->fields[F_CAMMODE], 0); in cal_camerarx_enable()
113 /* Always enable all lanes at the phy control level */ in cal_camerarx_enable()
114 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1); in cal_camerarx_enable()
116 if (phy->fields[F_CSI_MODE]) in cal_camerarx_enable()
117 regmap_field_write(phy->fields[F_CSI_MODE], 1); in cal_camerarx_enable()
118 regmap_field_write(phy->fields[F_CTRLCLKEN], 1); in cal_camerarx_enable()
121 void cal_camerarx_disable(struct cal_camerarx *phy) in cal_camerarx_disable() argument
123 regmap_field_write(phy->fields[F_CTRLCLKEN], 0); in cal_camerarx_disable()
133 static void cal_camerarx_config(struct cal_camerarx *phy, s64 link_freq) in cal_camerarx_config() argument
142 phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term); in cal_camerarx_config()
146 phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle); in cal_camerarx_config()
148 reg0 = camerarx_read(phy, CAL_CSI2_PHY_REG0); in cal_camerarx_config()
154 phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0); in cal_camerarx_config()
155 camerarx_write(phy, CAL_CSI2_PHY_REG0, reg0); in cal_camerarx_config()
157 reg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1); in cal_camerarx_config()
164 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1); in cal_camerarx_config()
165 camerarx_write(phy, CAL_CSI2_PHY_REG1, reg1); in cal_camerarx_config()
168 static void cal_camerarx_power(struct cal_camerarx *phy, bool enable) in cal_camerarx_power() argument
176 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_power()
182 current_state = cal_read_field(phy->cal, in cal_camerarx_power()
183 CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_power()
193 phy_err(phy, "Failed to power %s complexio\n", in cal_camerarx_power()
197 static void cal_camerarx_wait_reset(struct cal_camerarx *phy) in cal_camerarx_wait_reset() argument
203 if (cal_read_field(phy->cal, in cal_camerarx_wait_reset()
204 CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_wait_reset()
211 if (cal_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_wait_reset()
214 phy_err(phy, "Timeout waiting for Complex IO reset done\n"); in cal_camerarx_wait_reset()
217 static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy) in cal_camerarx_wait_stop_state() argument
223 if (cal_read_field(phy->cal, in cal_camerarx_wait_stop_state()
224 CAL_CSI2_TIMING(phy->instance), in cal_camerarx_wait_stop_state()
230 if (cal_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance), in cal_camerarx_wait_stop_state()
232 phy_err(phy, "Timeout waiting for stop state\n"); in cal_camerarx_wait_stop_state()
235 static void cal_camerarx_enable_irqs(struct cal_camerarx *phy) in cal_camerarx_enable_irqs() argument
253 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), in cal_camerarx_enable_irqs()
254 CAL_HL_IRQ_CIO_MASK(phy->instance) | in cal_camerarx_enable_irqs()
255 CAL_HL_IRQ_VC_MASK(phy->instance)); in cal_camerarx_enable_irqs()
256 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), in cal_camerarx_enable_irqs()
258 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(phy->instance), in cal_camerarx_enable_irqs()
262 static void cal_camerarx_disable_irqs(struct cal_camerarx *phy) in cal_camerarx_disable_irqs() argument
265 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0), in cal_camerarx_disable_irqs()
266 CAL_HL_IRQ_CIO_MASK(phy->instance) | in cal_camerarx_disable_irqs()
267 CAL_HL_IRQ_VC_MASK(phy->instance)); in cal_camerarx_disable_irqs()
268 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0); in cal_camerarx_disable_irqs()
269 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(phy->instance), 0); in cal_camerarx_disable_irqs()
272 static void cal_camerarx_ppi_enable(struct cal_camerarx *phy) in cal_camerarx_ppi_enable() argument
274 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), in cal_camerarx_ppi_enable()
277 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), in cal_camerarx_ppi_enable()
281 static void cal_camerarx_ppi_disable(struct cal_camerarx *phy) in cal_camerarx_ppi_disable() argument
283 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), in cal_camerarx_ppi_disable()
287 static int cal_camerarx_start(struct cal_camerarx *phy) in cal_camerarx_start() argument
294 if (phy->enable_count > 0) { in cal_camerarx_start()
295 phy->enable_count++; in cal_camerarx_start()
299 link_freq = cal_camerarx_get_ext_link_freq(phy); in cal_camerarx_start()
303 ret = v4l2_subdev_call(phy->source, core, s_power, 1); in cal_camerarx_start()
304 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) { in cal_camerarx_start()
305 phy_err(phy, "power on failed in subdev\n"); in cal_camerarx_start()
309 cal_camerarx_enable_irqs(phy); in cal_camerarx_start()
312 * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP / in cal_camerarx_start()
318 * 1. Configure all CSI-2 low level protocol registers to be ready to in cal_camerarx_start()
319 * receive signals/data from the CSI-2 PHY. in cal_camerarx_start()
321 * i.-v. Configure the lanes position and polarity. in cal_camerarx_start()
323 cal_camerarx_lane_config(phy); in cal_camerarx_start()
326 * vi.-vii. Configure D-PHY mode, enable the required lanes and in cal_camerarx_start()
329 cal_camerarx_enable(phy); in cal_camerarx_start()
332 * 2. CSI PHY and link initialization sequence. in cal_camerarx_start()
334 * a. Deassert the CSI-2 PHY reset. Do not wait for reset completion in cal_camerarx_start()
336 * CSI-2 HS clock. in cal_camerarx_start()
338 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_start()
341 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n", in cal_camerarx_start()
342 phy->instance, in cal_camerarx_start()
343 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance))); in cal_camerarx_start()
346 camerarx_read(phy, CAL_CSI2_PHY_REG0); in cal_camerarx_start()
348 /* Program the PHY timing parameters. */ in cal_camerarx_start()
349 cal_camerarx_config(phy, link_freq); in cal_camerarx_start()
354 * The stop-state-counter is based on fclk cycles, and we always use in cal_camerarx_start()
355 * the x16 and x4 settings, so stop-state-timeout = in cal_camerarx_start()
356 * fclk-cycle * 16 * 4 * counter. in cal_camerarx_start()
358 * Stop-state-timeout must be more than 100us as per CSI-2 spec, so we in cal_camerarx_start()
361 sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4); in cal_camerarx_start()
363 val = cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)); in cal_camerarx_start()
368 cal_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val); in cal_camerarx_start()
369 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n", in cal_camerarx_start()
370 phy->instance, in cal_camerarx_start()
371 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance))); in cal_camerarx_start()
374 cal_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance), in cal_camerarx_start()
376 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n", in cal_camerarx_start()
377 phy->instance, in cal_camerarx_start()
378 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance))); in cal_camerarx_start()
381 * c. Connect pull-down on CSI-2 PHY link (using pad control). in cal_camerarx_start()
388 * d. Power up the CSI-2 PHY. in cal_camerarx_start()
391 cal_camerarx_power(phy, true); in cal_camerarx_start()
394 * Start the source to enable the CSI-2 HS clock. We can now wait for in cal_camerarx_start()
395 * CSI-2 PHY reset to complete. in cal_camerarx_start()
397 ret = v4l2_subdev_call(phy->source, video, s_stream, 1); in cal_camerarx_start()
399 v4l2_subdev_call(phy->source, core, s_power, 0); in cal_camerarx_start()
400 cal_camerarx_disable_irqs(phy); in cal_camerarx_start()
401 phy_err(phy, "stream on failed in subdev\n"); in cal_camerarx_start()
405 cal_camerarx_wait_reset(phy); in cal_camerarx_start()
408 cal_camerarx_wait_stop_state(phy); in cal_camerarx_start()
410 phy_dbg(1, phy, "CSI2_%u_REG1 = 0x%08x (bits 31-28 should be set)\n", in cal_camerarx_start()
411 phy->instance, camerarx_read(phy, CAL_CSI2_PHY_REG1)); in cal_camerarx_start()
414 * g. Disable pull-down on CSI-2 PHY link (using pad control). in cal_camerarx_start()
420 /* Finally, enable the PHY Protocol Interface (PPI). */ in cal_camerarx_start()
421 cal_camerarx_ppi_enable(phy); in cal_camerarx_start()
423 phy->enable_count++; in cal_camerarx_start()
428 static void cal_camerarx_stop(struct cal_camerarx *phy) in cal_camerarx_stop() argument
432 if (--phy->enable_count > 0) in cal_camerarx_stop()
435 cal_camerarx_ppi_disable(phy); in cal_camerarx_stop()
437 cal_camerarx_disable_irqs(phy); in cal_camerarx_stop()
439 cal_camerarx_power(phy, false); in cal_camerarx_stop()
442 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), in cal_camerarx_stop()
446 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset\n", in cal_camerarx_stop()
447 phy->instance, in cal_camerarx_stop()
448 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance))); in cal_camerarx_stop()
450 /* Disable the phy */ in cal_camerarx_stop()
451 cal_camerarx_disable(phy); in cal_camerarx_stop()
453 if (v4l2_subdev_call(phy->source, video, s_stream, 0)) in cal_camerarx_stop()
454 phy_err(phy, "stream off failed in subdev\n"); in cal_camerarx_stop()
456 ret = v4l2_subdev_call(phy->source, core, s_power, 0); in cal_camerarx_stop()
457 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) in cal_camerarx_stop()
458 phy_err(phy, "power off failed in subdev\n"); in cal_camerarx_stop()
465 * LDOs on the device are disabled if CSI-2 module is powered on
470 * Errata does not apply when CSI-2 module is powered off
480 void cal_camerarx_i913_errata(struct cal_camerarx *phy) in cal_camerarx_i913_errata() argument
482 u32 reg10 = camerarx_read(phy, CAL_CSI2_PHY_REG10); in cal_camerarx_i913_errata()
486 phy_dbg(1, phy, "CSI2_%d_REG10 = 0x%08x\n", phy->instance, reg10); in cal_camerarx_i913_errata()
487 camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10); in cal_camerarx_i913_errata()
491 struct cal_camerarx *phy) in cal_camerarx_regmap_init() argument
496 if (!cal->data) in cal_camerarx_regmap_init()
497 return -EINVAL; in cal_camerarx_regmap_init()
499 phy_data = &cal->data->camerarx[phy->instance]; in cal_camerarx_regmap_init()
503 .reg = cal->syscon_camerrx_offset, in cal_camerarx_regmap_init()
504 .lsb = phy_data->fields[i].lsb, in cal_camerarx_regmap_init()
505 .msb = phy_data->fields[i].msb, in cal_camerarx_regmap_init()
512 phy->fields[i] = devm_regmap_field_alloc(cal->dev, in cal_camerarx_regmap_init()
513 cal->syscon_camerrx, in cal_camerarx_regmap_init()
515 if (IS_ERR(phy->fields[i])) { in cal_camerarx_regmap_init()
517 return PTR_ERR(phy->fields[i]); in cal_camerarx_regmap_init()
524 static int cal_camerarx_parse_dt(struct cal_camerarx *phy) in cal_camerarx_parse_dt() argument
526 struct v4l2_fwnode_endpoint *endpoint = &phy->endpoint; in cal_camerarx_parse_dt()
533 * Find the endpoint node for the port corresponding to the PHY in cal_camerarx_parse_dt()
534 * instance, and parse its CSI-2-related properties. in cal_camerarx_parse_dt()
536 ep_node = of_graph_get_endpoint_by_regs(phy->cal->dev->of_node, in cal_camerarx_parse_dt()
537 phy->instance, 0); in cal_camerarx_parse_dt()
540 * The endpoint is not mandatory, not all PHY instances need to in cal_camerarx_parse_dt()
543 phy_dbg(3, phy, "Port has no endpoint\n"); in cal_camerarx_parse_dt()
547 endpoint->bus_type = V4L2_MBUS_CSI2_DPHY; in cal_camerarx_parse_dt()
550 phy_err(phy, "Failed to parse endpoint\n"); in cal_camerarx_parse_dt()
554 for (i = 0; i < endpoint->bus.mipi_csi2.num_data_lanes; i++) { in cal_camerarx_parse_dt()
555 unsigned int lane = endpoint->bus.mipi_csi2.data_lanes[i]; in cal_camerarx_parse_dt()
558 phy_err(phy, "Invalid position %u for data lane %u\n", in cal_camerarx_parse_dt()
560 ret = -EINVAL; in cal_camerarx_parse_dt()
568 data_lanes[i*2-1] = '\0'; in cal_camerarx_parse_dt()
570 phy_dbg(3, phy, in cal_camerarx_parse_dt()
571 "CSI-2 bus: clock lane <%u>, data lanes <%s>, flags 0x%08x\n", in cal_camerarx_parse_dt()
572 endpoint->bus.mipi_csi2.clock_lane, data_lanes, in cal_camerarx_parse_dt()
573 endpoint->bus.mipi_csi2.flags); in cal_camerarx_parse_dt()
576 phy->source_ep_node = of_graph_get_remote_endpoint(ep_node); in cal_camerarx_parse_dt()
577 phy->source_node = of_graph_get_port_parent(phy->source_ep_node); in cal_camerarx_parse_dt()
578 if (!phy->source_node) { in cal_camerarx_parse_dt()
579 phy_dbg(3, phy, "Can't get remote parent\n"); in cal_camerarx_parse_dt()
580 of_node_put(phy->source_ep_node); in cal_camerarx_parse_dt()
581 ret = -EINVAL; in cal_camerarx_parse_dt()
585 phy_dbg(1, phy, "Found connected device %pOFn\n", phy->source_node); in cal_camerarx_parse_dt()
592 /* ------------------------------------------------------------------
594 * ------------------------------------------------------------------
604 struct cal_camerarx *phy = to_cal_camerarx(sd); in cal_camerarx_sd_s_stream() local
611 ret = cal_camerarx_start(phy); in cal_camerarx_sd_s_stream()
613 cal_camerarx_stop(phy); in cal_camerarx_sd_s_stream()
625 if (cal_rx_pad_is_source(code->pad)) { in cal_camerarx_sd_enum_mbus_code()
628 if (code->index > 0) in cal_camerarx_sd_enum_mbus_code()
629 return -EINVAL; in cal_camerarx_sd_enum_mbus_code()
633 code->code = fmt->code; in cal_camerarx_sd_enum_mbus_code()
635 if (code->index >= cal_num_formats) in cal_camerarx_sd_enum_mbus_code()
636 return -EINVAL; in cal_camerarx_sd_enum_mbus_code()
638 code->code = cal_formats[code->index].code; in cal_camerarx_sd_enum_mbus_code()
650 if (fse->index > 0) in cal_camerarx_sd_enum_frame_size()
651 return -EINVAL; in cal_camerarx_sd_enum_frame_size()
654 if (cal_rx_pad_is_source(fse->pad)) { in cal_camerarx_sd_enum_frame_size()
659 if (fse->code != fmt->code) in cal_camerarx_sd_enum_frame_size()
660 return -EINVAL; in cal_camerarx_sd_enum_frame_size()
662 fse->min_width = fmt->width; in cal_camerarx_sd_enum_frame_size()
663 fse->max_width = fmt->width; in cal_camerarx_sd_enum_frame_size()
664 fse->min_height = fmt->height; in cal_camerarx_sd_enum_frame_size()
665 fse->max_height = fmt->height; in cal_camerarx_sd_enum_frame_size()
667 fmtinfo = cal_format_by_code(fse->code); in cal_camerarx_sd_enum_frame_size()
669 return -EINVAL; in cal_camerarx_sd_enum_frame_size()
671 fse->min_width = CAL_MIN_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); in cal_camerarx_sd_enum_frame_size()
672 fse->max_width = CAL_MAX_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); in cal_camerarx_sd_enum_frame_size()
673 fse->min_height = CAL_MIN_HEIGHT_LINES; in cal_camerarx_sd_enum_frame_size()
674 fse->max_height = CAL_MAX_HEIGHT_LINES; in cal_camerarx_sd_enum_frame_size()
689 if (cal_rx_pad_is_source(format->pad)) in cal_camerarx_sd_set_fmt()
696 fmtinfo = cal_format_by_code(format->format.code); in cal_camerarx_sd_set_fmt()
700 /* Clamp the size, update the code. The colorspace is accepted as-is. */ in cal_camerarx_sd_set_fmt()
701 bpp = ALIGN(fmtinfo->bpp, 8); in cal_camerarx_sd_set_fmt()
703 format->format.width = clamp_t(unsigned int, format->format.width, in cal_camerarx_sd_set_fmt()
706 format->format.height = clamp_t(unsigned int, format->format.height, in cal_camerarx_sd_set_fmt()
709 format->format.code = fmtinfo->code; in cal_camerarx_sd_set_fmt()
710 format->format.field = V4L2_FIELD_NONE; in cal_camerarx_sd_set_fmt()
715 *fmt = format->format; in cal_camerarx_sd_set_fmt()
719 *fmt = format->format; in cal_camerarx_sd_set_fmt()
749 struct cal_camerarx *phy = to_cal_camerarx(sd); in cal_camerarx_get_frame_desc() local
754 remote_pad = media_pad_remote_pad_first(&phy->pads[CAL_CAMERARX_PAD_SINK]); in cal_camerarx_get_frame_desc()
756 return -EPIPE; in cal_camerarx_get_frame_desc()
758 ret = v4l2_subdev_call(phy->source, pad, get_frame_desc, in cal_camerarx_get_frame_desc()
759 remote_pad->index, &remote_desc); in cal_camerarx_get_frame_desc()
764 cal_err(phy->cal, in cal_camerarx_get_frame_desc()
765 "Frame descriptor does not describe CSI-2 link"); in cal_camerarx_get_frame_desc()
766 return -EINVAL; in cal_camerarx_get_frame_desc()
770 cal_err(phy->cal, in cal_camerarx_get_frame_desc()
773 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2; in cal_camerarx_get_frame_desc()
774 fd->num_entries = 1; in cal_camerarx_get_frame_desc()
775 fd->entry[0] = remote_desc.entry[0]; in cal_camerarx_get_frame_desc()
805 /* ------------------------------------------------------------------
807 * ------------------------------------------------------------------
813 struct platform_device *pdev = to_platform_device(cal->dev); in cal_camerarx_create()
814 struct cal_camerarx *phy; in cal_camerarx_create() local
819 phy = devm_kzalloc(cal->dev, sizeof(*phy), GFP_KERNEL); in cal_camerarx_create()
820 if (!phy) in cal_camerarx_create()
821 return ERR_PTR(-ENOMEM); in cal_camerarx_create()
823 phy->cal = cal; in cal_camerarx_create()
824 phy->instance = instance; in cal_camerarx_create()
826 spin_lock_init(&phy->vc_lock); in cal_camerarx_create()
828 phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in cal_camerarx_create()
832 phy->base = devm_ioremap_resource(cal->dev, phy->res); in cal_camerarx_create()
833 if (IS_ERR(phy->base)) { in cal_camerarx_create()
835 return ERR_CAST(phy->base); in cal_camerarx_create()
838 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n", in cal_camerarx_create()
839 phy->res->name, &phy->res->start, &phy->res->end); in cal_camerarx_create()
841 ret = cal_camerarx_regmap_init(cal, phy); in cal_camerarx_create()
845 ret = cal_camerarx_parse_dt(phy); in cal_camerarx_create()
850 sd = &phy->subdev; in cal_camerarx_create()
852 sd->internal_ops = &cal_camerarx_internal_ops; in cal_camerarx_create()
853 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; in cal_camerarx_create()
854 sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE; in cal_camerarx_create()
855 snprintf(sd->name, sizeof(sd->name), "CAMERARX%u", instance); in cal_camerarx_create()
856 sd->dev = cal->dev; in cal_camerarx_create()
858 phy->pads[CAL_CAMERARX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; in cal_camerarx_create()
860 phy->pads[i].flags = MEDIA_PAD_FL_SOURCE; in cal_camerarx_create()
861 sd->entity.ops = &cal_camerarx_media_ops; in cal_camerarx_create()
862 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(phy->pads), in cal_camerarx_create()
863 phy->pads); in cal_camerarx_create()
871 ret = v4l2_device_register_subdev(&cal->v4l2_dev, sd); in cal_camerarx_create()
875 return phy; in cal_camerarx_create()
880 media_entity_cleanup(&phy->subdev.entity); in cal_camerarx_create()
882 of_node_put(phy->source_ep_node); in cal_camerarx_create()
883 of_node_put(phy->source_node); in cal_camerarx_create()
887 void cal_camerarx_destroy(struct cal_camerarx *phy) in cal_camerarx_destroy() argument
889 if (!phy) in cal_camerarx_destroy()
892 v4l2_device_unregister_subdev(&phy->subdev); in cal_camerarx_destroy()
893 v4l2_subdev_cleanup(&phy->subdev); in cal_camerarx_destroy()
894 media_entity_cleanup(&phy->subdev.entity); in cal_camerarx_destroy()
895 of_node_put(phy->source_ep_node); in cal_camerarx_destroy()
896 of_node_put(phy->source_node); in cal_camerarx_destroy()