Lines Matching +full:chrom +full:- +full:art
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
8 * based on s5p-g2d
17 #include "dma2d-regs.h"
37 reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START); in dma2d_start()
42 return reg_read(d->regs, DMA2D_ISR_REG); in dma2d_get_int()
47 u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG); in dma2d_clear_int()
49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); in dma2d_clear_int()
55 reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK, in dma2d_config_common()
58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); in dma2d_config_common()
64 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE); in dma2d_config_out()
65 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE); in dma2d_config_out()
66 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE); in dma2d_config_out()
67 reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE); in dma2d_config_out()
68 reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE); in dma2d_config_out()
70 if (frm->fmt->cmode >= CM_MODE_ARGB8888 && in dma2d_config_out()
71 frm->fmt->cmode <= CM_MODE_ARGB4444) in dma2d_config_out()
72 reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK, in dma2d_config_out()
73 frm->fmt->cmode); in dma2d_config_out()
75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr); in dma2d_config_out()
77 reg_write(d->regs, DMA2D_OCOLR_REG, in dma2d_config_out()
78 (frm->a_rgb[3] << 24) | in dma2d_config_out()
79 (frm->a_rgb[2] << 16) | in dma2d_config_out()
80 (frm->a_rgb[1] << 8) | in dma2d_config_out()
81 frm->a_rgb[0]); in dma2d_config_out()
83 reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK, in dma2d_config_out()
84 frm->line_offset & 0x3fff); in dma2d_config_out()
90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); in dma2d_config_fg()
91 reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK, in dma2d_config_fg()
92 frm->line_offset); in dma2d_config_fg()
94 if (frm->fmt->cmode >= CM_MODE_ARGB8888 && in dma2d_config_fg()
95 frm->fmt->cmode <= CM_MODE_A4) in dma2d_config_fg()
96 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK, in dma2d_config_fg()
97 frm->fmt->cmode); in dma2d_config_fg()
99 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK, in dma2d_config_fg()
100 (frm->a_mode << 16) & 0x03); in dma2d_config_fg()
102 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK, in dma2d_config_fg()
103 frm->a_rgb[3] << 24); in dma2d_config_fg()
105 reg_write(d->regs, DMA2D_FGCOLR_REG, in dma2d_config_fg()
106 (frm->a_rgb[2] << 16) | in dma2d_config_fg()
107 (frm->a_rgb[1] << 8) | in dma2d_config_fg()
108 frm->a_rgb[0]); in dma2d_config_fg()
114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); in dma2d_config_bg()
115 reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK, in dma2d_config_bg()
116 frm->line_offset); in dma2d_config_bg()
118 if (frm->fmt->cmode >= CM_MODE_ARGB8888 && in dma2d_config_bg()
119 frm->fmt->cmode <= CM_MODE_A4) in dma2d_config_bg()
120 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK, in dma2d_config_bg()
121 frm->fmt->cmode); in dma2d_config_bg()
123 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK, in dma2d_config_bg()
124 (frm->a_mode << 16) & 0x03); in dma2d_config_bg()
126 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK, in dma2d_config_bg()
127 frm->a_rgb[3] << 24); in dma2d_config_bg()
129 reg_write(d->regs, DMA2D_BGCOLR_REG, in dma2d_config_bg()
130 (frm->a_rgb[2] << 16) | in dma2d_config_bg()
131 (frm->a_rgb[1] << 8) | in dma2d_config_bg()
132 frm->a_rgb[0]); in dma2d_config_bg()