Lines Matching +full:0 +full:x209c
20 #define S5P_FIMV_START_ADDR 0x0000
21 #define S5P_FIMV_END_ADDR 0xe008
23 #define S5P_FIMV_SW_RESET 0x0000
24 #define S5P_FIMV_RISC_HOST_INT 0x0008
27 #define S5P_FIMV_HOST2RISC_CMD 0x0030
28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034
29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038
30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c
31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040
34 #define S5P_FIMV_RISC2HOST_CMD 0x0044
35 #define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF
36 #define S5P_FIMV_RISC2HOST_ARG1 0x0048
37 #define S5P_FIMV_RISC2HOST_ARG2 0x004c
38 #define S5P_FIMV_RISC2HOST_ARG3 0x0050
39 #define S5P_FIMV_RISC2HOST_ARG4 0x0054
41 #define S5P_FIMV_FW_VERSION 0x0058
42 #define S5P_FIMV_SYS_MEM_SZ 0x005c
43 #define S5P_FIMV_FW_STATUS 0x0080
46 #define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508
47 #define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c
48 #define S5P_FIMV_MC_STATUS 0x0510
51 #define S5P_FIMV_COMMON_BASE_A 0x0600
52 #define S5P_FIMV_COMMON_BASE_B 0x0700
59 #define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
61 #define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
63 #define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)
67 #define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
69 #define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
71 #define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
73 #define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
75 #define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)
79 #define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
80 #define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
81 #define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
82 #define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
85 #define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
86 #define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
87 #define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
88 #define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
89 #define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)
91 #define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)
93 #define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)
97 #define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)
98 #define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)
101 #define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04)
103 #define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10)
104 #define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08)
105 #define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14)
106 #define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c)
111 #define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
113 #define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08)
115 #define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
117 #define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40)
123 #define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
129 #define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
131 #define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
134 #define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */
135 #define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */
137 #define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */
138 #define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */
141 #define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */
142 #define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */
143 #define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */
144 #define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
148 #define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
150 #define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
151 #define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */
152 #define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */
153 #define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */
154 #define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */
155 #define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */
158 #define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */
159 #define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */
160 #define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */
162 #define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */
163 #define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */
164 #define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the
166 #define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */
167 #define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */
169 #define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to
171 #define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */
173 #define S5P_FIMV_SI_DECODE_Y_ADR 0x2024 /* luma addr of decoded pic */
174 #define S5P_FIMV_SI_DECODE_C_ADR 0x2028 /* chroma addrof decoded pic */
175 #define S5P_FIMV_SI_DECODE_STATUS 0x202c /* status of decoded picture */
177 #define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */
178 #define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */
179 #define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */
180 #define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */
181 #define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */
183 #define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */
184 #define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */
185 #define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */
186 #define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */
187 #define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */
189 #define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
191 #define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
193 #define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
195 #define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
199 #define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0
204 #define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3)
207 #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4)
211 #define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5)
220 #define S5P_FIMV_DECODE_Y_ADR 0x2024
221 #define S5P_FIMV_DECODE_C_ADR 0x2028
224 #define S5P_FIMV_DECODE_FRAME_TYPE 0x2020
227 #define S5P_FIMV_DECODE_FRAME_SKIPPED 0
254 #define S5P_FIMV_ENC_UPMV_SIZE 0x10000
255 #define S5P_FIMV_ENC_COLFLG_SIZE 0x10000
256 #define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000
257 #define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000
258 #define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000
259 #define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000
262 #define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */
263 #define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */
264 #define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */
265 #define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
266 #define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0
272 #define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded
274 #define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded
277 #define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */
278 #define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */
279 #define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */
280 #define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */
281 #define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */
283 #define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */
284 #define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */
285 #define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */
286 #define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */
287 #define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */
289 #define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */
290 #define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */
291 #define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */
292 #define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */
293 #define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */
294 #define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */
295 #define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */
296 #define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */
298 #define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */
299 #define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */
300 #define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */
301 #define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */
302 #define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */
305 #define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */
306 #define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */
307 #define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */
308 #define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */
309 #define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &
312 #define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */
315 #define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */
318 #define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */
322 #define S5P_FIMV_DDELAY_VAL_MASK 0xff
324 #define S5P_FIMV_DPB_COUNT_MASK 0xffff
329 #define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */
330 #define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */
335 #define S5P_FIMV_CODEC_H264_DEC 0
357 #define S5P_FIMV_H2R_CMD_EMPTY 0
365 #define S5P_FIMV_R2H_CMD_EMPTY 0
389 #define S5P_FIMV_REG_CLEAR_BEGIN 0
390 #define S5P_FIMV_REG_CLEAR_COUNT 0
397 #define S5P_FIMV_ERR_DEC_MASK 0xFFFF
398 #define S5P_FIMV_ERR_DEC_SHIFT 0
399 #define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000
406 #define S5P_FIMV_SHARED_CROP_INFO_H 0x0020
407 #define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF
408 #define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0
409 #define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000
411 #define S5P_FIMV_SHARED_CROP_INFO_V 0x0024
412 #define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF
413 #define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0
414 #define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000
416 #define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004
417 #define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008
418 #define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C
419 #define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018
420 #define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030
421 #define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064
422 #define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068
423 #define S5P_FIMV_SHARED_MV_SIZE 0x006C
424 #define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010
425 #define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014
426 #define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028
427 #define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070
428 #define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074
429 #define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
430 #define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
431 #define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
447 #define MFC_VERSION 0x51
450 #define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL 0x16C
451 #define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID 0x170
452 #define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO 0x174
453 #define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS 0x178