Lines Matching +full:mode +full:- +full:reg
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P G2D - 2D Graphics Accelerator Driver
10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
24 #define SRC_MSK_DIRECT_REG 0x0204 /* Src and Mask Direction reg */
25 #define DST_PAT_DIRECT_REG 0x0208 /* Dest and Pattern Direction reg */
28 #define SRC_SELECT_REG 0x0300 /* Src Image Selection reg */
29 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
30 #define SRC_STRIDE_REG 0x0308 /* Src Stride reg */
31 #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */
32 #define SRC_LEFT_TOP_REG 0x0310 /* Src Left Top Coordinate reg */
33 #define SRC_RIGHT_BOTTOM_REG 0x0314 /* Src Right Bottom Coordinate reg */
39 #define DST_SELECT_REG 0x0400 /* Dest Image Selection reg */
40 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
41 #define DST_STRIDE_REG 0x0408 /* Dest Stride reg */
42 #define DST_COLOR_MODE_REG 0x040C /* Dest Image Color Mode reg */
43 #define DST_LEFT_TOP_REG 0x0410 /* Dest Left Top Coordinate reg */
44 #define DST_RIGHT_BOTTOM_REG 0x0414 /* Dest Right Bottom Coordinate reg */
47 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
48 #define PAT_SIZE_REG 0x0504 /* Pattern Image Size reg */
49 #define PAT_COLOR_MODE_REG 0x0508 /* Pattern Image Color Mode reg */
50 #define PAT_OFFSET_REG 0x050C /* Pattern Left Top Coordinate reg */
51 #define PAT_STRIDE_REG 0x0510 /* Pattern Stride reg */
54 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
55 #define MASK_STRIDE_REG 0x0524 /* Mask Stride reg */
63 #define THIRD_OPERAND_REG 0x0610 /* Third Operand Selection reg */
64 #define ROP4_REG 0x0614 /* Raster Operation reg */
68 #define FG_COLOR_REG 0x0700 /* Foreground Color reg */
69 #define BG_COLOR_REG 0x0704 /* Background Color reg */
70 #define BS_COLOR_REG 0x0708 /* Blue Screen Color reg */
73 #define SRC_COLORKEY_CTRL_REG 0x0710 /* Src Colorkey control reg */
75 Min reg */
77 Max reg */
78 #define DST_COLORKEY_CTRL_REG 0x071C /* Dest Colorkey control reg */
80 Min reg */
82 Max reg */
84 /* Color mode values */
117 /* Command mode register values */