1 // SPDX-License-Identifier: GPL-2.0-only
3  * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
12 #include <media/drv-intf/exynos-fimc.h>
14 #include "fimc-lite-reg.h"
15 #include "fimc-lite.h"
16 #include "fimc-core.h"
25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
49 	u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_get_interrupt_source()
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
66 	if (atomic_read(&dev->out_path) == FIMC_IO_DMA) {  in flite_hw_set_interrupt_mask()
72 		/* An output to the FIMC-IS */  in flite_hw_set_interrupt_mask()
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
129 	u32 pixelcode = f->fmt->mbus_code;  in flite_hw_set_source_format()
133 	while (--i) {  in flite_hw_set_source_format()
139 		v4l2_err(&dev->ve.vdev,  in flite_hw_set_source_format()
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
152 	cfg |= (f->f_width << 16) | f->f_height;  in flite_hw_set_source_format()
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
165 	cfg |= (f->rect.left << 16) | f->rect.top;  in flite_hw_set_window_offset()
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
169 	hoff2 = f->f_width - f->rect.width - f->rect.left;  in flite_hw_set_window_offset()
170 	voff2 = f->f_height - f->rect.height - f->rect.top;  in flite_hw_set_window_offset()
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);  in flite_hw_set_window_offset()
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
192 	unsigned int flags = si->flags;  in flite_hw_set_camera_bus()
194 	if (si->sensor_bus_type != FIMC_BUS_TYPE_MIPI_CSI2) {  in flite_hw_set_camera_bus()
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
214 	flite_hw_set_camera_port(dev, si->mux_id);  in flite_hw_set_camera_bus()
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
238 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
241 	while (--i)  in flite_hw_set_out_order()
242 		if (pixcode[i][0] == f->fmt->mbus_code)  in flite_hw_set_out_order()
245 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
253 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
255 	cfg |= (f->f_height << 16) | f->f_width;  in flite_hw_set_dma_window()
256 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
259 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
261 	cfg |= (f->rect.top << 16) | f->rect.left;  in flite_hw_set_dma_window()
262 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
270 	if (dev->dd->max_dma_bufs == 1)  in flite_hw_set_dma_buffer()
273 		index = buf->index;  in flite_hw_set_dma_buffer()
276 		writel(buf->addr, dev->regs + FLITE_REG_CIOSA);  in flite_hw_set_dma_buffer()
278 		writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));  in flite_hw_set_dma_buffer()
280 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
282 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
289 	if (dev->dd->max_dma_bufs == 1)  in flite_hw_mask_dma_buffer()
292 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
294 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
301 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
305 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
310 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
340 	v4l2_info(&dev->subdev, "--- %s ---\n", label);  in flite_hw_dump_regs()
343 		u32 cfg = readl(dev->regs + registers[i].offset);  in flite_hw_dump_regs()
344 		v4l2_info(&dev->subdev, "%9s: 0x%08x\n",  in flite_hw_dump_regs()