Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
23 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WPF_IRQ_ENB_UNDE BIT(16)
36 #define VI6_WPF_IRQ_ENB_DFEE BIT(1)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
40 #define VI6_WPF_IRQ_STA_UND BIT(16)
41 #define VI6_WPF_IRQ_STA_DFE BIT(1)
42 #define VI6_WPF_IRQ_STA_FRE BIT(0)
45 #define VI6_DISP_IRQ_ENB_DSTE BIT(8)
46 #define VI6_DISP_IRQ_ENB_MAEE BIT(5)
47 #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n)
50 #define VI6_DISP_IRQ_STA_DST BIT(8)
51 #define VI6_DISP_IRQ_STA_MAE BIT(5)
52 #define VI6_DISP_IRQ_STA_LNE(n) BIT(n)
57 /* -----------------------------------------------------------------------------
64 #define VI6_DL_CTRL_DC2 BIT(12)
65 #define VI6_DL_CTRL_DC1 BIT(8)
66 #define VI6_DL_CTRL_DC0 BIT(4)
67 #define VI6_DL_CTRL_CFM0 BIT(2)
68 #define VI6_DL_CTRL_NH0 BIT(1)
69 #define VI6_DL_CTRL_DLE BIT(0)
74 #define VI6_DL_SWAP_LWS BIT(2)
75 #define VI6_DL_SWAP_WDS BIT(1)
76 #define VI6_DL_SWAP_BTS BIT(0)
79 #define VI6_DL_EXT_CTRL_NWE BIT(16)
80 #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8)
81 #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8
82 #define VI6_DL_EXT_CTRL_DLPRI BIT(5)
83 #define VI6_DL_EXT_CTRL_EXPRI BIT(4)
84 #define VI6_DL_EXT_CTRL_EXT BIT(0)
86 #define VI6_DL_EXT_AUTOFLD_INT BIT(0)
89 #define VI6_DL_BODY_SIZE_UPD BIT(24)
93 /* -----------------------------------------------------------------------------
112 #define VI6_RPF_INFMT_VIR BIT(28)
113 #define VI6_RPF_INFMT_CIPM BIT(16)
114 #define VI6_RPF_INFMT_SPYCS BIT(15)
115 #define VI6_RPF_INFMT_SPUVS BIT(14)
125 #define VI6_RPF_INFMT_CSC BIT(8)
130 #define VI6_RPF_DSWAP_A_LLS BIT(11)
131 #define VI6_RPF_DSWAP_A_LWS BIT(10)
132 #define VI6_RPF_DSWAP_A_WDS BIT(9)
133 #define VI6_RPF_DSWAP_A_BTS BIT(8)
134 #define VI6_RPF_DSWAP_P_LLS BIT(3)
135 #define VI6_RPF_DSWAP_P_LWS BIT(2)
136 #define VI6_RPF_DSWAP_P_WDS BIT(1)
137 #define VI6_RPF_DSWAP_P_BTS BIT(0)
155 #define VI6_RPF_ALPH_SEL_BSEL BIT(23)
160 #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8)
161 #define VI6_RPF_ALPH_SEL_ALPHA1_SHIFT 8
170 #define VI6_RPF_VRTCOL_SET_LAYG_MASK (0xff << 8)
171 #define VI6_RPF_VRTCOL_SET_LAYG_SHIFT 8
176 #define VI6_RPF_MSK_CTRL_MSK_EN BIT(24)
179 #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8)
180 #define VI6_RPF_MSK_CTRL_MGG_SHIFT 8
190 #define VI6_RPF_MSK_SET_MSG_MASK (0xff << 8)
191 #define VI6_RPF_MSK_SET_MSG_SHIFT 8
196 #define VI6_RPF_CKEY_CTRL_CV BIT(4)
197 #define VI6_RPF_CKEY_CTRL_SAPE1 BIT(1)
198 #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0)
206 #define VI6_RPF_CKEY_SET_GY_MASK (0xff << 8)
207 #define VI6_RPF_CKEY_SET_GY_SHIFT 8
226 #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8)
227 #define VI6_RPF_MULT_ALPHA_P_MMD_RATIO (1 << 8)
228 #define VI6_RPF_MULT_ALPHA_P_MMD_IMAGE (2 << 8)
229 #define VI6_RPF_MULT_ALPHA_P_MMD_BOTH (3 << 8)
234 #define VI6_RPF_EXT_INFMT0_F2B BIT(12)
235 #define VI6_RPF_EXT_INFMT0_IPBD_Y_8 (0 << 8)
236 #define VI6_RPF_EXT_INFMT0_IPBD_Y_10 (1 << 8)
237 #define VI6_RPF_EXT_INFMT0_IPBD_Y_12 (2 << 8)
245 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
249 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
252 #define VI6_RPF_BRDITH_CTRL_ODE BIT(8)
253 #define VI6_RPF_BRDITH_CTRL_CBRM BIT(0)
255 /* -----------------------------------------------------------------------------
277 #define VI6_WPF_SZCLIP_EN BIT(28)
286 #define VI6_WPF_OUTFMT_PXA BIT(23)
287 #define VI6_WPF_OUTFMT_ROT BIT(18)
288 #define VI6_WPF_OUTFMT_HFLP BIT(17)
289 #define VI6_WPF_OUTFMT_FLP BIT(16)
290 #define VI6_WPF_OUTFMT_SPYCS BIT(15)
291 #define VI6_WPF_OUTFMT_SPUVS BIT(14)
300 #define VI6_WPF_OUTFMT_CSC BIT(8)
305 #define VI6_WPF_DSWAP_P_LLS BIT(3)
306 #define VI6_WPF_DSWAP_P_LWS BIT(2)
307 #define VI6_WPF_DSWAP_P_WDS BIT(1)
308 #define VI6_WPF_DSWAP_P_BTS BIT(0)
311 #define VI6_WPF_RNDCTRL_CBRM BIT(28)
324 #define VI6_WPF_ROT_CTRL_LN16 BIT(17)
335 #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0)
337 /* -----------------------------------------------------------------------------
344 #define VI6_UIF_DISCOM_DOCMCR_CMPRU BIT(16)
345 #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0)
348 #define VI6_UIF_DISCOM_DOCMSTR_CMPPRE BIT(1)
349 #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0)
352 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE BIT(1)
353 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0)
356 #define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN BIT(1)
357 #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0)
364 #define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n) ((n) << 8)
365 #define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF BIT(7)
375 /* -----------------------------------------------------------------------------
382 #define VI6_DPR_WPF_FPORCH_FP_WPFN (5 << 8)
392 #define VI6_DPR_ROUTE_BRSSEL BIT(28)
395 #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8)
396 #define VI6_DPR_ROUTE_FP_SHIFT 8
402 #define VI6_DPR_SMPPT_TGW_MASK (7 << 8)
403 #define VI6_DPR_SMPPT_TGW_SHIFT 8
424 /* -----------------------------------------------------------------------------
431 #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8)
432 #define VI6_SRU_CTRL0_PARAM1_SHIFT 8
434 #define VI6_SRU_CTRL0_PARAM2 BIT(3)
435 #define VI6_SRU_CTRL0_PARAM3 BIT(2)
436 #define VI6_SRU_CTRL0_PARAM4 BIT(1)
437 #define VI6_SRU_CTRL0_EN BIT(0)
444 #define VI6_SRU_CTRL2_PARAM7_SHIFT 8
447 /* -----------------------------------------------------------------------------
454 #define VI6_UDS_CTRL_AMD BIT(30)
455 #define VI6_UDS_CTRL_FMD BIT(29)
456 #define VI6_UDS_CTRL_BLADV BIT(28)
457 #define VI6_UDS_CTRL_AON BIT(25)
458 #define VI6_UDS_CTRL_ATHON BIT(24)
459 #define VI6_UDS_CTRL_BC BIT(20)
460 #define VI6_UDS_CTRL_NE_A BIT(19)
461 #define VI6_UDS_CTRL_NE_RCR BIT(18)
462 #define VI6_UDS_CTRL_NE_GY BIT(17)
463 #define VI6_UDS_CTRL_NE_BCB BIT(16)
464 #define VI6_UDS_CTRL_AMDSLH BIT(2)
465 #define VI6_UDS_CTRL_TDIPC BIT(1)
478 #define VI6_UDS_ALPTH_TH1_MASK (0xff << 8)
479 #define VI6_UDS_ALPTH_TH1_SHIFT 8
486 #define VI6_UDS_ALPVAL_VAL1_MASK (0xff << 8)
487 #define VI6_UDS_ALPVAL_VAL1_SHIFT 8
504 #define VI6_UDS_IPC_FIELD BIT(27)
509 #define VI6_UDS_HSZCLIP_HCEN BIT(28)
524 #define VI6_UDS_FILL_COLOR_GFILC_MASK (0xff << 8)
525 #define VI6_UDS_FILL_COLOR_GFILC_SHIFT 8
529 /* -----------------------------------------------------------------------------
534 #define VI6_LUT_CTRL_EN BIT(0)
536 /* -----------------------------------------------------------------------------
541 #define VI6_CLU_CTRL_AAI BIT(28)
542 #define VI6_CLU_CTRL_MVS BIT(24)
545 #define VI6_CLU_CTRL_OS0_2D (3 << 8)
548 #define VI6_CLU_CTRL_M2D BIT(1)
549 #define VI6_CLU_CTRL_EN BIT(0)
551 /* -----------------------------------------------------------------------------
556 #define VI6_HST_CTRL_EN BIT(0)
558 /* -----------------------------------------------------------------------------
563 #define VI6_HSI_CTRL_EN BIT(0)
565 /* -----------------------------------------------------------------------------
577 #define VI6_ROP_NOR 8
590 #define VI6_BRU_INCTRL_NRM BIT(28)
618 #define VI6_BRU_VIRRPF_COL_GY_MASK (0xff << 8)
619 #define VI6_BRU_VIRRPF_COL_GY_SHIFT 8
623 #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4))
624 #define VI6_BRU_CTRL_RBC BIT(31)
636 #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4))
637 #define VI6_BRU_BLD_CBES BIT(31)
651 #define VI6_BRU_BLD_ABES BIT(23)
664 #define VI6_BRU_BLD_COEFX_MASK (0xff << 8)
665 #define VI6_BRU_BLD_COEFX_SHIFT 8
678 /* -----------------------------------------------------------------------------
689 #define VI6_HGO_MODE_STEP BIT(10)
690 #define VI6_HGO_MODE_MAXRGB BIT(7)
691 #define VI6_HGO_MODE_OFSB_R BIT(6)
692 #define VI6_HGO_MODE_OFSB_G BIT(5)
693 #define VI6_HGO_MODE_OFSB_B BIT(4)
697 #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8)
698 #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8)
714 #define VI6_HGO_REGRST_RCLEA BIT(0)
716 /* -----------------------------------------------------------------------------
733 #define VI6_HGT_LBn_H(n) (0x3428 + (n) * 8)
734 #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8)
740 #define VI6_HGT_REGRST_RCLEA BIT(0)
742 /* -----------------------------------------------------------------------------
746 #define VI6_LIF_OFFSET (-0x100)
751 #define VI6_LIF_CTRL_CFMT BIT(4)
752 #define VI6_LIF_CTRL_REQSEL BIT(1)
753 #define VI6_LIF_CTRL_LIF_EN BIT(0)
762 #define VI6_LIF_LBA_LBA0 BIT(31)
766 /* -----------------------------------------------------------------------------
773 /* -----------------------------------------------------------------------------
779 #define VI6_IP_VERSION_MODEL_MASK (0xff << 8)
780 #define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8)
781 #define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8)
782 #define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8)
783 #define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8)
784 #define VI6_IP_VERSION_MODEL_VSPS_V2H (0x12 << 8)
785 #define VI6_IP_VERSION_MODEL_VSPD_V2H (0x13 << 8)
786 #define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8)
787 #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8)
788 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8)
789 #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8)
790 #define VI6_IP_VERSION_MODEL_VSPD_V3 (0x18 << 8)
791 #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8)
792 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8)
793 #define VI6_IP_VERSION_MODEL_VSPD_GEN4 (0x1c << 8)
795 #define VI6_IP_VERSION_MODEL_VSPD_RZG2L (0x80 << 8)
815 /* -----------------------------------------------------------------------------
821 /* -----------------------------------------------------------------------------
827 /* -----------------------------------------------------------------------------
834 /* -----------------------------------------------------------------------------