Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WPF_IRQ_ENB_UNDE BIT(16)
36 #define VI6_WPF_IRQ_ENB_DFEE BIT(1)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
40 #define VI6_WPF_IRQ_STA_UND BIT(16)
41 #define VI6_WPF_IRQ_STA_DFE BIT(1)
42 #define VI6_WPF_IRQ_STA_FRE BIT(0)
45 #define VI6_DISP_IRQ_ENB_DSTE BIT(8)
46 #define VI6_DISP_IRQ_ENB_MAEE BIT(5)
47 #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n)
50 #define VI6_DISP_IRQ_STA_DST BIT(8)
51 #define VI6_DISP_IRQ_STA_MAE BIT(5)
52 #define VI6_DISP_IRQ_STA_LNE(n) BIT(n)
57 /* -----------------------------------------------------------------------------
62 #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16)
63 #define VI6_DL_CTRL_AR_WAIT_SHIFT 16
64 #define VI6_DL_CTRL_DC2 BIT(12)
65 #define VI6_DL_CTRL_DC1 BIT(8)
66 #define VI6_DL_CTRL_DC0 BIT(4)
67 #define VI6_DL_CTRL_CFM0 BIT(2)
68 #define VI6_DL_CTRL_NH0 BIT(1)
69 #define VI6_DL_CTRL_DLE BIT(0)
74 #define VI6_DL_SWAP_LWS BIT(2)
75 #define VI6_DL_SWAP_WDS BIT(1)
76 #define VI6_DL_SWAP_BTS BIT(0)
79 #define VI6_DL_EXT_CTRL_NWE BIT(16)
82 #define VI6_DL_EXT_CTRL_DLPRI BIT(5)
83 #define VI6_DL_EXT_CTRL_EXPRI BIT(4)
84 #define VI6_DL_EXT_CTRL_EXT BIT(0)
86 #define VI6_DL_EXT_AUTOFLD_INT BIT(0)
89 #define VI6_DL_BODY_SIZE_UPD BIT(24)
93 /* -----------------------------------------------------------------------------
100 #define VI6_RPF_SRC_BSIZE_BHSIZE_MASK (0x1fff << 16)
101 #define VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT 16
106 #define VI6_RPF_SRC_ESIZE_EHSIZE_MASK (0x1fff << 16)
107 #define VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT 16
112 #define VI6_RPF_INFMT_VIR BIT(28)
113 #define VI6_RPF_INFMT_CIPM BIT(16)
114 #define VI6_RPF_INFMT_SPYCS BIT(15)
115 #define VI6_RPF_INFMT_SPUVS BIT(14)
125 #define VI6_RPF_INFMT_CSC BIT(8)
130 #define VI6_RPF_DSWAP_A_LLS BIT(11)
131 #define VI6_RPF_DSWAP_A_LWS BIT(10)
132 #define VI6_RPF_DSWAP_A_WDS BIT(9)
133 #define VI6_RPF_DSWAP_A_BTS BIT(8)
134 #define VI6_RPF_DSWAP_P_LLS BIT(3)
135 #define VI6_RPF_DSWAP_P_LWS BIT(2)
136 #define VI6_RPF_DSWAP_P_WDS BIT(1)
137 #define VI6_RPF_DSWAP_P_BTS BIT(0)
140 #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16)
141 #define VI6_RPF_LOC_HCOORD_SHIFT 16
155 #define VI6_RPF_ALPH_SEL_BSEL BIT(23)
168 #define VI6_RPF_VRTCOL_SET_LAYR_MASK (0xff << 16)
169 #define VI6_RPF_VRTCOL_SET_LAYR_SHIFT 16
176 #define VI6_RPF_MSK_CTRL_MSK_EN BIT(24)
177 #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16)
178 #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16
188 #define VI6_RPF_MSK_SET_MSR_MASK (0xff << 16)
189 #define VI6_RPF_MSK_SET_MSR_SHIFT 16
196 #define VI6_RPF_CKEY_CTRL_CV BIT(4)
197 #define VI6_RPF_CKEY_CTRL_SAPE1 BIT(1)
198 #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0)
204 #define VI6_RPF_CKEY_SET_R_MASK (0xff << 16)
205 #define VI6_RPF_CKEY_SET_R_SHIFT 16
212 #define VI6_RPF_SRCM_PSTRIDE_Y_SHIFT 16
234 #define VI6_RPF_EXT_INFMT0_F2B BIT(12)
245 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
249 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
252 #define VI6_RPF_BRDITH_CTRL_ODE BIT(8)
253 #define VI6_RPF_BRDITH_CTRL_CBRM BIT(0)
255 /* -----------------------------------------------------------------------------
277 #define VI6_WPF_SZCLIP_EN BIT(28)
278 #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16)
279 #define VI6_WPF_SZCLIP_OFST_SHIFT 16
286 #define VI6_WPF_OUTFMT_PXA BIT(23)
287 #define VI6_WPF_OUTFMT_ROT BIT(18)
288 #define VI6_WPF_OUTFMT_HFLP BIT(17)
289 #define VI6_WPF_OUTFMT_FLP BIT(16)
290 #define VI6_WPF_OUTFMT_SPYCS BIT(15)
291 #define VI6_WPF_OUTFMT_SPUVS BIT(14)
300 #define VI6_WPF_OUTFMT_CSC BIT(8)
305 #define VI6_WPF_DSWAP_P_LLS BIT(3)
306 #define VI6_WPF_DSWAP_P_LWS BIT(2)
307 #define VI6_WPF_DSWAP_P_WDS BIT(1)
308 #define VI6_WPF_DSWAP_P_BTS BIT(0)
311 #define VI6_WPF_RNDCTRL_CBRM BIT(28)
316 #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16)
317 #define VI6_WPF_RNDCTRL_ATHRESH_SHIFT 16
324 #define VI6_WPF_ROT_CTRL_LN16 BIT(17)
335 #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0)
337 /* -----------------------------------------------------------------------------
344 #define VI6_UIF_DISCOM_DOCMCR_CMPRU BIT(16)
345 #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0)
348 #define VI6_UIF_DISCOM_DOCMSTR_CMPPRE BIT(1)
349 #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0)
352 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE BIT(1)
353 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0)
356 #define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN BIT(1)
357 #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0)
360 #define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n) ((n) << 16)
365 #define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF BIT(7)
375 /* -----------------------------------------------------------------------------
392 #define VI6_DPR_ROUTE_BRSSEL BIT(28)
393 #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16)
394 #define VI6_DPR_ROUTE_FXA_SHIFT 16
411 #define VI6_DPR_NODE_SRU 16
424 /* -----------------------------------------------------------------------------
429 #define VI6_SRU_CTRL0_PARAM0_MASK (0x1ff << 16)
430 #define VI6_SRU_CTRL0_PARAM0_SHIFT 16
434 #define VI6_SRU_CTRL0_PARAM2 BIT(3)
435 #define VI6_SRU_CTRL0_PARAM3 BIT(2)
436 #define VI6_SRU_CTRL0_PARAM4 BIT(1)
437 #define VI6_SRU_CTRL0_EN BIT(0)
443 #define VI6_SRU_CTRL2_PARAM6_SHIFT 16
447 /* -----------------------------------------------------------------------------
454 #define VI6_UDS_CTRL_AMD BIT(30)
455 #define VI6_UDS_CTRL_FMD BIT(29)
456 #define VI6_UDS_CTRL_BLADV BIT(28)
457 #define VI6_UDS_CTRL_AON BIT(25)
458 #define VI6_UDS_CTRL_ATHON BIT(24)
459 #define VI6_UDS_CTRL_BC BIT(20)
460 #define VI6_UDS_CTRL_NE_A BIT(19)
461 #define VI6_UDS_CTRL_NE_RCR BIT(18)
462 #define VI6_UDS_CTRL_NE_GY BIT(17)
463 #define VI6_UDS_CTRL_NE_BCB BIT(16)
464 #define VI6_UDS_CTRL_AMDSLH BIT(2)
465 #define VI6_UDS_CTRL_TDIPC BIT(1)
470 #define VI6_UDS_SCALE_HFRAC_MASK (0xfff << 16)
471 #define VI6_UDS_SCALE_HFRAC_SHIFT 16
484 #define VI6_UDS_ALPVAL_VAL2_MASK (0xff << 16)
485 #define VI6_UDS_ALPVAL_VAL2_SHIFT 16
492 #define VI6_UDS_PASS_BWIDTH_H_MASK (0x7f << 16)
493 #define VI6_UDS_PASS_BWIDTH_H_SHIFT 16
498 #define VI6_UDS_HPHASE_HSTP_MASK (0xfff << 16)
499 #define VI6_UDS_HPHASE_HSTP_SHIFT 16
504 #define VI6_UDS_IPC_FIELD BIT(27)
509 #define VI6_UDS_HSZCLIP_HCEN BIT(28)
510 #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16)
511 #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT 16
516 #define VI6_UDS_CLIP_SIZE_HSIZE_MASK (0x1fff << 16)
517 #define VI6_UDS_CLIP_SIZE_HSIZE_SHIFT 16
522 #define VI6_UDS_FILL_COLOR_RFILC_MASK (0xff << 16)
523 #define VI6_UDS_FILL_COLOR_RFILC_SHIFT 16
529 /* -----------------------------------------------------------------------------
534 #define VI6_LUT_CTRL_EN BIT(0)
536 /* -----------------------------------------------------------------------------
541 #define VI6_CLU_CTRL_AAI BIT(28)
542 #define VI6_CLU_CTRL_MVS BIT(24)
548 #define VI6_CLU_CTRL_M2D BIT(1)
549 #define VI6_CLU_CTRL_EN BIT(0)
551 /* -----------------------------------------------------------------------------
556 #define VI6_HST_CTRL_EN BIT(0)
558 /* -----------------------------------------------------------------------------
563 #define VI6_HSI_CTRL_EN BIT(0)
565 /* -----------------------------------------------------------------------------
590 #define VI6_BRU_INCTRL_NRM BIT(28)
591 #define VI6_BRU_INCTRL_DnON (1 << (16 + (n)))
602 #define VI6_BRU_VIRRPF_SIZE_HSIZE_MASK (0x1fff << 16)
603 #define VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT 16
608 #define VI6_BRU_VIRRPF_LOC_HCOORD_MASK (0x1fff << 16)
609 #define VI6_BRU_VIRRPF_LOC_HCOORD_SHIFT 16
616 #define VI6_BRU_VIRRPF_COL_RCR_MASK (0xff << 16)
617 #define VI6_BRU_VIRRPF_COL_RCR_SHIFT 16
624 #define VI6_BRU_CTRL_RBC BIT(31)
628 #define VI6_BRU_CTRL_SRCSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 16)
629 #define VI6_BRU_CTRL_SRCSEL_VRPF (4 << 16)
630 #define VI6_BRU_CTRL_SRCSEL_MASK (7 << 16)
637 #define VI6_BRU_BLD_CBES BIT(31)
651 #define VI6_BRU_BLD_ABES BIT(23)
658 #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16)
659 #define VI6_BRU_BLD_ACMDY_255_DST_A (1 << 16)
660 #define VI6_BRU_BLD_ACMDY_SRC_A (2 << 16)
661 #define VI6_BRU_BLD_ACMDY_255_SRC_A (3 << 16)
662 #define VI6_BRU_BLD_ACMDY_COEFY (4 << 16)
663 #define VI6_BRU_BLD_ACMDY_MASK (7 << 16)
678 /* -----------------------------------------------------------------------------
683 #define VI6_HGO_OFFSET_HOFFSET_SHIFT 16
686 #define VI6_HGO_SIZE_HSIZE_SHIFT 16
689 #define VI6_HGO_MODE_STEP BIT(10)
690 #define VI6_HGO_MODE_MAXRGB BIT(7)
691 #define VI6_HGO_MODE_OFSB_R BIT(6)
692 #define VI6_HGO_MODE_OFSB_G BIT(5)
693 #define VI6_HGO_MODE_OFSB_B BIT(4)
714 #define VI6_HGO_REGRST_RCLEA BIT(0)
716 /* -----------------------------------------------------------------------------
721 #define VI6_HGT_OFFSET_HOFFSET_SHIFT 16
724 #define VI6_HGT_SIZE_HSIZE_SHIFT 16
730 #define VI6_HGT_HUE_AREA_LOWER_SHIFT 16
740 #define VI6_HGT_REGRST_RCLEA BIT(0)
742 /* -----------------------------------------------------------------------------
746 #define VI6_LIF_OFFSET (-0x100)
749 #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16)
750 #define VI6_LIF_CTRL_OBTH_SHIFT 16
751 #define VI6_LIF_CTRL_CFMT BIT(4)
752 #define VI6_LIF_CTRL_REQSEL BIT(1)
753 #define VI6_LIF_CTRL_LIF_EN BIT(0)
756 #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16)
757 #define VI6_LIF_CSBTH_HBTH_SHIFT 16
762 #define VI6_LIF_LBA_LBA0 BIT(31)
763 #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16)
764 #define VI6_LIF_LBA_LBA1_SHIFT 16
766 /* -----------------------------------------------------------------------------
773 /* -----------------------------------------------------------------------------
813 #define VI6_IP_VERSION_VSP_SW (0xfffe << 16) /* SW VSP version */
815 /* -----------------------------------------------------------------------------
821 /* -----------------------------------------------------------------------------
827 /* -----------------------------------------------------------------------------
834 /* -----------------------------------------------------------------------------