Lines Matching +full:all +full:- +full:inputs
1 // SPDX-License-Identifier: GPL-2.0+
3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
11 #include <linux/dma-mapping.h>
14 #include <media/media-entity.h>
15 #include <media/v4l2-subdev.h>
27 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
29 /* -----------------------------------------------------------------------------
38 if (drm_pipe->du_complete) { in vsp1_du_pipeline_frame_end()
39 struct vsp1_entity *uif = drm_pipe->uif; in vsp1_du_pipeline_frame_end()
45 crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0; in vsp1_du_pipeline_frame_end()
46 drm_pipe->du_complete(drm_pipe->du_private, status, crc); in vsp1_du_pipeline_frame_end()
50 drm_pipe->force_brx_release = false; in vsp1_du_pipeline_frame_end()
51 wake_up(&drm_pipe->wait_queue); in vsp1_du_pipeline_frame_end()
55 /* -----------------------------------------------------------------------------
79 prev->sink = next; in vsp1_du_insert_uif()
80 prev->sink_pad = next_pad; in vsp1_du_insert_uif()
84 prev->sink = uif; in vsp1_du_insert_uif()
85 prev->sink_pad = UIF_PAD_SINK; in vsp1_du_insert_uif()
89 ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format); in vsp1_du_insert_uif()
95 ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format); in vsp1_du_insert_uif()
99 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n", in vsp1_du_insert_uif()
108 uif->sink = next; in vsp1_du_insert_uif()
109 uif->sink_pad = next_pad; in vsp1_du_insert_uif()
134 crop = &vsp1->drm->inputs[rpf->entity.index].crop; in vsp1_du_pipeline_setup_rpf()
137 format.format.width = crop->width + crop->left; in vsp1_du_pipeline_setup_rpf()
138 format.format.height = crop->height + crop->top; in vsp1_du_pipeline_setup_rpf()
139 format.format.code = rpf->fmtinfo->mbus; in vsp1_du_pipeline_setup_rpf()
142 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_rpf()
147 dev_dbg(vsp1->dev, in vsp1_du_pipeline_setup_rpf()
150 format.format.code, rpf->entity.index); in vsp1_du_pipeline_setup_rpf()
156 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL, in vsp1_du_pipeline_setup_rpf()
161 dev_dbg(vsp1->dev, in vsp1_du_pipeline_setup_rpf()
164 rpf->entity.index); in vsp1_du_pipeline_setup_rpf()
172 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL, in vsp1_du_pipeline_setup_rpf()
177 dev_dbg(vsp1->dev, in vsp1_du_pipeline_setup_rpf()
180 format.format.code, rpf->entity.index); in vsp1_du_pipeline_setup_rpf()
184 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_rpf()
190 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE, in vsp1_du_pipeline_setup_rpf()
191 pipe->brx, brx_input); in vsp1_du_pipeline_setup_rpf()
198 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_rpf()
203 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n", in vsp1_du_pipeline_setup_rpf()
205 format.format.code, BRX_NAME(pipe->brx), format.pad); in vsp1_du_pipeline_setup_rpf()
209 sel.r = vsp1->drm->inputs[rpf->entity.index].compose; in vsp1_du_pipeline_setup_rpf()
211 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL, in vsp1_du_pipeline_setup_rpf()
216 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n", in vsp1_du_pipeline_setup_rpf()
218 BRX_NAME(pipe->brx), sel.pad); in vsp1_du_pipeline_setup_rpf()
240 * - If we need more than two inputs, use the BRU. in vsp1_du_pipeline_setup_brx()
241 * - Otherwise, if we are not forced to release our BRx, keep it. in vsp1_du_pipeline_setup_brx()
242 * - Else, use any free BRx (randomly starting with the BRU). in vsp1_du_pipeline_setup_brx()
244 if (pipe->num_inputs > 2) in vsp1_du_pipeline_setup_brx()
245 brx = &vsp1->bru->entity; in vsp1_du_pipeline_setup_brx()
246 else if (pipe->brx && !drm_pipe->force_brx_release) in vsp1_du_pipeline_setup_brx()
247 brx = pipe->brx; in vsp1_du_pipeline_setup_brx()
248 else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe) in vsp1_du_pipeline_setup_brx()
249 brx = &vsp1->bru->entity; in vsp1_du_pipeline_setup_brx()
251 brx = &vsp1->brs->entity; in vsp1_du_pipeline_setup_brx()
254 if (brx != pipe->brx) { in vsp1_du_pipeline_setup_brx()
258 if (pipe->brx) { in vsp1_du_pipeline_setup_brx()
259 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n", in vsp1_du_pipeline_setup_brx()
260 __func__, pipe->lif->index, in vsp1_du_pipeline_setup_brx()
261 BRX_NAME(pipe->brx)); in vsp1_du_pipeline_setup_brx()
277 released_brx = pipe->brx; in vsp1_du_pipeline_setup_brx()
279 list_del(&pipe->brx->list_pipe); in vsp1_du_pipeline_setup_brx()
280 pipe->brx->sink = NULL; in vsp1_du_pipeline_setup_brx()
281 pipe->brx->pipe = NULL; in vsp1_du_pipeline_setup_brx()
282 pipe->brx = NULL; in vsp1_du_pipeline_setup_brx()
289 if (brx->pipe) { in vsp1_du_pipeline_setup_brx()
292 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n", in vsp1_du_pipeline_setup_brx()
293 __func__, pipe->lif->index, BRX_NAME(brx)); in vsp1_du_pipeline_setup_brx()
295 owner_pipe = to_vsp1_drm_pipeline(brx->pipe); in vsp1_du_pipeline_setup_brx()
296 owner_pipe->force_brx_release = true; in vsp1_du_pipeline_setup_brx()
298 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe); in vsp1_du_pipeline_setup_brx()
299 vsp1_du_pipeline_configure(&owner_pipe->pipe); in vsp1_du_pipeline_setup_brx()
301 ret = wait_event_timeout(owner_pipe->wait_queue, in vsp1_du_pipeline_setup_brx()
302 !owner_pipe->force_brx_release, in vsp1_du_pipeline_setup_brx()
305 dev_warn(vsp1->dev, in vsp1_du_pipeline_setup_brx()
307 owner_pipe->pipe.lif->index); in vsp1_du_pipeline_setup_brx()
316 if (released_brx && !released_brx->pipe) in vsp1_du_pipeline_setup_brx()
317 list_add_tail(&released_brx->list_pipe, in vsp1_du_pipeline_setup_brx()
318 &pipe->entities); in vsp1_du_pipeline_setup_brx()
324 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n", in vsp1_du_pipeline_setup_brx()
325 __func__, pipe->lif->index, BRX_NAME(brx)); in vsp1_du_pipeline_setup_brx()
327 pipe->brx = brx; in vsp1_du_pipeline_setup_brx()
328 pipe->brx->pipe = pipe; in vsp1_du_pipeline_setup_brx()
329 pipe->brx->sink = &pipe->output->entity; in vsp1_du_pipeline_setup_brx()
330 pipe->brx->sink_pad = 0; in vsp1_du_pipeline_setup_brx()
332 list_add_tail(&pipe->brx->list_pipe, in vsp1_du_pipeline_setup_brx()
333 &pipe->output->entity.list_pipe); in vsp1_du_pipeline_setup_brx()
342 format.pad = brx->source_pad; in vsp1_du_pipeline_setup_brx()
343 format.format.width = drm_pipe->width; in vsp1_du_pipeline_setup_brx()
344 format.format.height = drm_pipe->height; in vsp1_du_pipeline_setup_brx()
347 ret = v4l2_subdev_call(&brx->subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_brx()
352 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n", in vsp1_du_pipeline_setup_brx()
354 format.format.code, BRX_NAME(brx), brx->source_pad); in vsp1_du_pipeline_setup_brx()
356 if (format.format.width != drm_pipe->width || in vsp1_du_pipeline_setup_brx()
357 format.format.height != drm_pipe->height) { in vsp1_du_pipeline_setup_brx()
358 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__); in vsp1_du_pipeline_setup_brx()
359 return -EPIPE; in vsp1_du_pipeline_setup_brx()
367 return vsp1->drm->inputs[rpf->entity.index].zpos; in rpf_zpos()
375 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, }; in vsp1_du_pipeline_setup_inputs() local
382 /* Count the number of enabled inputs and sort them by Z-order. */ in vsp1_du_pipeline_setup_inputs()
383 pipe->num_inputs = 0; in vsp1_du_pipeline_setup_inputs()
385 for (i = 0; i < vsp1->info->rpf_count; ++i) { in vsp1_du_pipeline_setup_inputs()
386 struct vsp1_rwpf *rpf = vsp1->rpf[i]; in vsp1_du_pipeline_setup_inputs()
389 if (!pipe->inputs[i]) in vsp1_du_pipeline_setup_inputs()
393 for (j = pipe->num_inputs++; j > 0; --j) { in vsp1_du_pipeline_setup_inputs()
394 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf)) in vsp1_du_pipeline_setup_inputs()
396 inputs[j] = inputs[j-1]; in vsp1_du_pipeline_setup_inputs()
399 inputs[j] = rpf; in vsp1_du_pipeline_setup_inputs()
409 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__, in vsp1_du_pipeline_setup_inputs()
410 BRX_NAME(pipe->brx)); in vsp1_du_pipeline_setup_inputs()
414 brx = to_brx(&pipe->brx->subdev); in vsp1_du_pipeline_setup_inputs()
417 for (i = 0; i < pipe->brx->source_pad; ++i) { in vsp1_du_pipeline_setup_inputs()
418 struct vsp1_rwpf *rpf = inputs[i]; in vsp1_du_pipeline_setup_inputs()
421 brx->inputs[i].rpf = NULL; in vsp1_du_pipeline_setup_inputs()
425 if (!rpf->entity.pipe) { in vsp1_du_pipeline_setup_inputs()
426 rpf->entity.pipe = pipe; in vsp1_du_pipeline_setup_inputs()
427 list_add(&rpf->entity.list_pipe, &pipe->entities); in vsp1_du_pipeline_setup_inputs()
430 brx->inputs[i].rpf = rpf; in vsp1_du_pipeline_setup_inputs()
431 rpf->brx_input = i; in vsp1_du_pipeline_setup_inputs()
432 rpf->entity.sink = pipe->brx; in vsp1_du_pipeline_setup_inputs()
433 rpf->entity.sink_pad = i; in vsp1_du_pipeline_setup_inputs()
435 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n", in vsp1_du_pipeline_setup_inputs()
436 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i); in vsp1_du_pipeline_setup_inputs()
438 uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE && in vsp1_du_pipeline_setup_inputs()
439 drm_pipe->crc.index == i ? drm_pipe->uif : NULL; in vsp1_du_pipeline_setup_inputs()
444 dev_err(vsp1->dev, in vsp1_du_pipeline_setup_inputs()
446 __func__, rpf->entity.index); in vsp1_du_pipeline_setup_inputs()
452 uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL; in vsp1_du_pipeline_setup_inputs()
456 pipe->brx, pipe->brx->source_pad, in vsp1_du_pipeline_setup_inputs()
457 &pipe->output->entity, 0); in vsp1_du_pipeline_setup_inputs()
459 dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n", in vsp1_du_pipeline_setup_inputs()
460 __func__, BRX_NAME(pipe->brx)); in vsp1_du_pipeline_setup_inputs()
463 if (!drm_pipe->uif) in vsp1_du_pipeline_setup_inputs()
474 drm_pipe->uif->pipe = NULL; in vsp1_du_pipeline_setup_inputs()
475 } else if (!drm_pipe->uif->pipe) { in vsp1_du_pipeline_setup_inputs()
476 drm_pipe->uif->pipe = pipe; in vsp1_du_pipeline_setup_inputs()
477 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities); in vsp1_du_pipeline_setup_inputs()
494 format.format.width = drm_pipe->width; in vsp1_du_pipeline_setup_output()
495 format.format.height = drm_pipe->height; in vsp1_du_pipeline_setup_output()
499 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_output()
504 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n", in vsp1_du_pipeline_setup_output()
506 format.format.code, pipe->output->entity.index); in vsp1_du_pipeline_setup_output()
509 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL, in vsp1_du_pipeline_setup_output()
514 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n", in vsp1_du_pipeline_setup_output()
516 format.format.code, pipe->output->entity.index); in vsp1_du_pipeline_setup_output()
519 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_output()
524 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n", in vsp1_du_pipeline_setup_output()
526 format.format.code, pipe->lif->index); in vsp1_du_pipeline_setup_output()
532 if (format.format.width != drm_pipe->width || in vsp1_du_pipeline_setup_output()
533 format.format.height != drm_pipe->height || in vsp1_du_pipeline_setup_output()
535 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__, in vsp1_du_pipeline_setup_output()
536 pipe->lif->index); in vsp1_du_pipeline_setup_output()
537 return -EPIPE; in vsp1_du_pipeline_setup_output()
543 /* Configure all entities in the pipeline. */
553 vsp1_pipeline_calculate_partition(pipe, &pipe->part_table[0], in vsp1_du_pipeline_configure()
554 drm_pipe->width, 0); in vsp1_du_pipeline_configure()
556 if (drm_pipe->force_brx_release) in vsp1_du_pipeline_configure()
558 if (pipe->output->writeback) in vsp1_du_pipeline_configure()
561 dl = vsp1_dl_list_get(pipe->output->dlm); in vsp1_du_pipeline_configure()
564 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) { in vsp1_du_pipeline_configure()
566 if (!entity->pipe) { in vsp1_du_pipeline_configure()
567 vsp1_dl_body_write(dlb, entity->route->reg, in vsp1_du_pipeline_configure()
570 entity->sink = NULL; in vsp1_du_pipeline_configure()
571 list_del(&entity->list_pipe); in vsp1_du_pipeline_configure()
577 vsp1_entity_configure_stream(entity, entity->state, pipe, in vsp1_du_pipeline_configure()
581 &pipe->part_table[0], dl, dlb); in vsp1_du_pipeline_configure()
596 dev_dbg(vsp1->dev, "Unsupported pixel format %08x\n", in vsp1_du_pipeline_set_rwpf_format()
598 return -EINVAL; in vsp1_du_pipeline_set_rwpf_format()
603 * All formats with two planes have a horizontal subsampling value of 2, in vsp1_du_pipeline_set_rwpf_format()
607 chroma_hsub = (fmtinfo->planes == 3) ? fmtinfo->hsub : 1; in vsp1_du_pipeline_set_rwpf_format()
609 rwpf->fmtinfo = fmtinfo; in vsp1_du_pipeline_set_rwpf_format()
610 rwpf->format.num_planes = fmtinfo->planes; in vsp1_du_pipeline_set_rwpf_format()
611 rwpf->format.plane_fmt[0].bytesperline = pitch; in vsp1_du_pipeline_set_rwpf_format()
612 rwpf->format.plane_fmt[1].bytesperline = pitch / chroma_hsub; in vsp1_du_pipeline_set_rwpf_format()
617 /* -----------------------------------------------------------------------------
626 return -EPROBE_DEFER; in vsp1_du_init()
633 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
646 * configuration of its sink 0 pad, we also set up the formats on all blend unit
663 if (pipe_index >= vsp1->info->lif_count) in vsp1_du_setup_lif()
664 return -EINVAL; in vsp1_du_setup_lif()
666 drm_pipe = &vsp1->drm->pipe[pipe_index]; in vsp1_du_setup_lif()
667 pipe = &drm_pipe->pipe; in vsp1_du_setup_lif()
672 mutex_lock(&vsp1->drm->lock); in vsp1_du_setup_lif()
674 brx = to_brx(&pipe->brx->subdev); in vsp1_du_setup_lif()
681 if (ret == -ETIMEDOUT) in vsp1_du_setup_lif()
682 dev_err(vsp1->dev, "DRM pipeline stop timeout\n"); in vsp1_du_setup_lif()
684 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) { in vsp1_du_setup_lif()
685 struct vsp1_rwpf *rpf = pipe->inputs[i]; in vsp1_du_setup_lif()
692 * inputs. in vsp1_du_setup_lif()
694 WARN_ON(!rpf->entity.pipe); in vsp1_du_setup_lif()
695 rpf->entity.pipe = NULL; in vsp1_du_setup_lif()
696 list_del(&rpf->entity.list_pipe); in vsp1_du_setup_lif()
697 pipe->inputs[i] = NULL; in vsp1_du_setup_lif()
699 brx->inputs[rpf->brx_input].rpf = NULL; in vsp1_du_setup_lif()
702 drm_pipe->du_complete = NULL; in vsp1_du_setup_lif()
703 pipe->num_inputs = 0; in vsp1_du_setup_lif()
705 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n", in vsp1_du_setup_lif()
706 __func__, pipe->lif->index, in vsp1_du_setup_lif()
707 BRX_NAME(pipe->brx)); in vsp1_du_setup_lif()
709 list_del(&pipe->brx->list_pipe); in vsp1_du_setup_lif()
710 pipe->brx->pipe = NULL; in vsp1_du_setup_lif()
711 pipe->brx = NULL; in vsp1_du_setup_lif()
713 mutex_unlock(&vsp1->drm->lock); in vsp1_du_setup_lif()
715 vsp1_dlm_reset(pipe->output->dlm); in vsp1_du_setup_lif()
718 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__); in vsp1_du_setup_lif()
724 pipe->underrun_count = 0; in vsp1_du_setup_lif()
726 drm_pipe->width = cfg->width; in vsp1_du_setup_lif()
727 drm_pipe->height = cfg->height; in vsp1_du_setup_lif()
728 pipe->interlaced = cfg->interlaced; in vsp1_du_setup_lif()
730 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n", in vsp1_du_setup_lif()
731 __func__, pipe_index, cfg->width, cfg->height, in vsp1_du_setup_lif()
732 pipe->interlaced ? "i" : ""); in vsp1_du_setup_lif()
734 mutex_lock(&vsp1->drm->lock); in vsp1_du_setup_lif()
756 drm_pipe->du_complete = cfg->callback; in vsp1_du_setup_lif()
757 drm_pipe->du_private = cfg->callback_data; in vsp1_du_setup_lif()
763 /* Configure all entities in the pipeline. */ in vsp1_du_setup_lif()
767 mutex_unlock(&vsp1->drm->lock); in vsp1_du_setup_lif()
773 spin_lock_irqsave(&pipe->irqlock, flags); in vsp1_du_setup_lif()
775 spin_unlock_irqrestore(&pipe->irqlock, flags); in vsp1_du_setup_lif()
777 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__); in vsp1_du_setup_lif()
784 * vsp1_du_atomic_begin - Prepare for an atomic update
794 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
797 * @rpf_index: index of the RPF to setup (0-based)
803 * composition rectangle. The Z-order is configurable with higher @zpos values
812 * @cfg.pitch value is expressed in bytes and applies to all planes for
828 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index]; in vsp1_du_atomic_update()
832 if (rpf_index >= vsp1->info->rpf_count) in vsp1_du_atomic_update()
833 return -EINVAL; in vsp1_du_atomic_update()
835 rpf = vsp1->rpf[rpf_index]; in vsp1_du_atomic_update()
838 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__, in vsp1_du_atomic_update()
842 * Remove the RPF from the pipeline's inputs. Keep it in the in vsp1_du_atomic_update()
846 rpf->entity.pipe = NULL; in vsp1_du_atomic_update()
847 drm_pipe->pipe.inputs[rpf_index] = NULL; in vsp1_du_atomic_update()
851 dev_dbg(vsp1->dev, in vsp1_du_atomic_update()
852 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n", in vsp1_du_atomic_update()
854 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height, in vsp1_du_atomic_update()
855 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height, in vsp1_du_atomic_update()
856 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1], in vsp1_du_atomic_update()
857 &cfg->mem[2], cfg->zpos); in vsp1_du_atomic_update()
861 * rectangles and Z-order position and for the input. in vsp1_du_atomic_update()
863 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, rpf, cfg->pixelformat, in vsp1_du_atomic_update()
864 cfg->pitch); in vsp1_du_atomic_update()
868 rpf->alpha = cfg->alpha; in vsp1_du_atomic_update()
870 rpf->mem.addr[0] = cfg->mem[0]; in vsp1_du_atomic_update()
871 rpf->mem.addr[1] = cfg->mem[1]; in vsp1_du_atomic_update()
872 rpf->mem.addr[2] = cfg->mem[2]; in vsp1_du_atomic_update()
874 rpf->format.flags = cfg->premult ? V4L2_PIX_FMT_FLAG_PREMUL_ALPHA : 0; in vsp1_du_atomic_update()
876 vsp1->drm->inputs[rpf_index].crop = cfg->src; in vsp1_du_atomic_update()
877 vsp1->drm->inputs[rpf_index].compose = cfg->dst; in vsp1_du_atomic_update()
878 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos; in vsp1_du_atomic_update()
880 drm_pipe->pipe.inputs[rpf_index] = rpf; in vsp1_du_atomic_update()
887 * vsp1_du_atomic_flush - Commit an atomic update
896 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index]; in vsp1_du_atomic_flush()
897 struct vsp1_pipeline *pipe = &drm_pipe->pipe; in vsp1_du_atomic_flush()
900 drm_pipe->crc = cfg->crc; in vsp1_du_atomic_flush()
902 mutex_lock(&vsp1->drm->lock); in vsp1_du_atomic_flush()
904 if (cfg->writeback.pixelformat) { in vsp1_du_atomic_flush()
905 const struct vsp1_du_writeback_config *wb_cfg = &cfg->writeback; in vsp1_du_atomic_flush()
907 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output, in vsp1_du_atomic_flush()
908 wb_cfg->pixelformat, in vsp1_du_atomic_flush()
909 wb_cfg->pitch); in vsp1_du_atomic_flush()
913 pipe->output->mem.addr[0] = wb_cfg->mem[0]; in vsp1_du_atomic_flush()
914 pipe->output->mem.addr[1] = wb_cfg->mem[1]; in vsp1_du_atomic_flush()
915 pipe->output->mem.addr[2] = wb_cfg->mem[2]; in vsp1_du_atomic_flush()
916 pipe->output->writeback = true; in vsp1_du_atomic_flush()
926 mutex_unlock(&vsp1->drm->lock); in vsp1_du_atomic_flush()
935 * As all the buffers allocated by the DU driver are coherent, we can in vsp1_du_map_sg()
937 * non-coherent buffers will be added to the DU driver. in vsp1_du_map_sg()
939 return dma_map_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE, in vsp1_du_map_sg()
948 dma_unmap_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE, in vsp1_du_unmap_sg()
953 /* -----------------------------------------------------------------------------
961 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL); in vsp1_drm_init()
962 if (!vsp1->drm) in vsp1_drm_init()
963 return -ENOMEM; in vsp1_drm_init()
965 mutex_init(&vsp1->drm->lock); in vsp1_drm_init()
968 for (i = 0; i < vsp1->info->lif_count; ++i) { in vsp1_drm_init()
969 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i]; in vsp1_drm_init()
970 struct vsp1_pipeline *pipe = &drm_pipe->pipe; in vsp1_drm_init()
972 init_waitqueue_head(&drm_pipe->wait_queue); in vsp1_drm_init()
976 pipe->partitions = 1; in vsp1_drm_init()
977 pipe->part_table = &drm_pipe->partition; in vsp1_drm_init()
979 pipe->frame_end = vsp1_du_pipeline_frame_end; in vsp1_drm_init()
985 pipe->output = vsp1->wpf[i]; in vsp1_drm_init()
986 pipe->lif = &vsp1->lif[i]->entity; in vsp1_drm_init()
988 pipe->output->entity.pipe = pipe; in vsp1_drm_init()
989 pipe->output->entity.sink = pipe->lif; in vsp1_drm_init()
990 pipe->output->entity.sink_pad = 0; in vsp1_drm_init()
991 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities); in vsp1_drm_init()
993 pipe->lif->pipe = pipe; in vsp1_drm_init()
994 list_add_tail(&pipe->lif->list_pipe, &pipe->entities); in vsp1_drm_init()
1000 if (i < vsp1->info->uif_count) in vsp1_drm_init()
1001 drm_pipe->uif = &vsp1->uif[i]->entity; in vsp1_drm_init()
1004 /* Disable all RPFs initially. */ in vsp1_drm_init()
1005 for (i = 0; i < vsp1->info->rpf_count; ++i) { in vsp1_drm_init()
1006 struct vsp1_rwpf *input = vsp1->rpf[i]; in vsp1_drm_init()
1008 INIT_LIST_HEAD(&input->entity.list_pipe); in vsp1_drm_init()
1016 mutex_destroy(&vsp1->drm->lock); in vsp1_drm_cleanup()