Lines Matching +full:0 +full:x00008020
49 #define FDP1_CAPTURE BIT(0)
65 #define FD1_CTL_CMD 0x0000
66 #define FD1_CTL_CMD_STRCMD BIT(0)
69 #define FD1_CTL_SGCMD 0x0004
70 #define FD1_CTL_SGCMD_SGEN BIT(0)
73 #define FD1_CTL_REGEND 0x0008
74 #define FD1_CTL_REGEND_REGEND BIT(0)
77 #define FD1_CTL_CHACT 0x000c
83 #define FD1_CTL_CHACT_RD0 BIT(0)
86 #define FD1_CTL_OPMODE 0x0010
88 #define FD1_CTL_OPMODE_VIMD_INTERRUPT (0 << 0)
89 #define FD1_CTL_OPMODE_VIMD_BESTEFFORT (1 << 0)
90 #define FD1_CTL_OPMODE_VIMD_NOINTERRUPT (2 << 0)
92 #define FD1_CTL_VPERIOD 0x0014
93 #define FD1_CTL_CLKCTRL 0x0018
94 #define FD1_CTL_CLKCTRL_CSTP_N BIT(0)
97 #define FD1_CTL_SRESET 0x001c
98 #define FD1_CTL_SRESET_SRST BIT(0)
101 #define FD1_CTL_STATUS 0x0024
107 #define FD1_CTL_STATUS_BSY BIT(0)
109 #define FD1_CTL_VCYCLE_STAT 0x0028
112 #define FD1_CTL_IRQENB 0x0038
114 #define FD1_CTL_IRQSTA 0x003c
116 #define FD1_CTL_IRQFSET 0x0040
121 #define FD1_CTL_IRQ_FREE BIT(0)
127 #define FD1_RPF_SIZE 0x0060
128 #define FD1_RPF_SIZE_MASK GENMASK(12, 0)
130 #define FD1_RPF_SIZE_V_SHIFT 0
132 #define FD1_RPF_FORMAT 0x0064
138 #define FD1_RPF_PSTRIDE 0x0068
140 #define FD1_RPF_PSTRIDE_C_SHIFT 0
143 #define FD1_RPF0_ADDR_Y 0x006c
146 #define FD1_RPF1_ADDR_Y 0x0078
147 #define FD1_RPF1_ADDR_C0 0x007c
148 #define FD1_RPF1_ADDR_C1 0x0080
151 #define FD1_RPF2_ADDR_Y 0x0084
153 #define FD1_RPF_SMSK_ADDR 0x0090
154 #define FD1_RPF_SWAP 0x0094
157 #define FD1_WPF_FORMAT 0x00c0
162 #define FD1_WPF_FORMAT_WRTM_601_16 (0 << 9)
167 #define FD1_WPF_RNDCTL 0x00c4
169 #define FD1_WPF_RNDCTL_CLMD_NOCLIP (0 << 12)
173 #define FD1_WPF_PSTRIDE 0x00c8
175 #define FD1_WPF_PSTRIDE_C_SHIFT 0
178 #define FD1_WPF_ADDR_Y 0x00cc
179 #define FD1_WPF_ADDR_C0 0x00d0
180 #define FD1_WPF_ADDR_C1 0x00d4
181 #define FD1_WPF_SWAP 0x00d8
182 #define FD1_WPF_SWAP_OSWAP_SHIFT 0
186 #define FD1_RWPF_SWAP_BYTE BIT(0)
192 #define FD1_IPC_MODE 0x0100
194 #define FD1_IPC_MODE_DIM_ADAPT2D3D (0 << 0)
195 #define FD1_IPC_MODE_DIM_FIXED2D (1 << 0)
196 #define FD1_IPC_MODE_DIM_FIXED3D (2 << 0)
197 #define FD1_IPC_MODE_DIM_PREVFIELD (3 << 0)
198 #define FD1_IPC_MODE_DIM_NEXTFIELD (4 << 0)
200 #define FD1_IPC_SMSK_THRESH 0x0104
201 #define FD1_IPC_SMSK_THRESH_CONST 0x00010002
203 #define FD1_IPC_COMB_DET 0x0108
204 #define FD1_IPC_COMB_DET_CONST 0x00200040
206 #define FD1_IPC_MOTDEC 0x010c
207 #define FD1_IPC_MOTDEC_CONST 0x00008020
210 #define FD1_IPC_DLI_BLEND 0x0120
211 #define FD1_IPC_DLI_BLEND_CONST 0x0080ff02
213 #define FD1_IPC_DLI_HGAIN 0x0124
214 #define FD1_IPC_DLI_HGAIN_CONST 0x001000ff
216 #define FD1_IPC_DLI_SPRS 0x0128
217 #define FD1_IPC_DLI_SPRS_CONST 0x009004ff
219 #define FD1_IPC_DLI_ANGLE 0x012c
220 #define FD1_IPC_DLI_ANGLE_CONST 0x0004080c
222 #define FD1_IPC_DLI_ISOPIX0 0x0130
223 #define FD1_IPC_DLI_ISOPIX0_CONST 0xff10ff10
225 #define FD1_IPC_DLI_ISOPIX1 0x0134
226 #define FD1_IPC_DLI_ISOPIX1_CONST 0x0000ff10
229 #define FD1_IPC_SENSOR_TH0 0x0140
230 #define FD1_IPC_SENSOR_TH0_CONST 0x20208080
232 #define FD1_IPC_SENSOR_TH1 0x0144
233 #define FD1_IPC_SENSOR_TH1_CONST 0
235 #define FD1_IPC_SENSOR_CTL0 0x0170
236 #define FD1_IPC_SENSOR_CTL0_CONST 0x00002201
238 #define FD1_IPC_SENSOR_CTL1 0x0174
239 #define FD1_IPC_SENSOR_CTL1_CONST 0
241 #define FD1_IPC_SENSOR_CTL2 0x0178
243 #define FD1_IPC_SENSOR_CTL2_Y_SHIFT 0
245 #define FD1_IPC_SENSOR_CTL3 0x017c
247 #define FD1_IPC_SENSOR_CTL3_1_SHIFT 0
250 #define FD1_IPC_LMEM 0x01e0
255 #define FD1_IP_INTDATA 0x0800
257 #define FD1_IP_GEN2 0x02010101
258 #define FD1_IP_M3W 0x02010202
259 #define FD1_IP_H3 0x02010203
260 #define FD1_IP_M3N 0x02010204
261 #define FD1_IP_E3 0x02010205
264 #define FD1_LUT_DIF_ADJ 0x1000
265 #define FD1_LUT_SAD_ADJ 0x1400
266 #define FD1_LUT_BLD_GAIN 0x1800
267 #define FD1_LUT_DIF_GAIN 0x1c00
268 #define FD1_LUT_MDET 0x2000
299 { V4L2_PIX_FMT_RGB332, { 8, 0, 0 }, 1, 1, 1, 0x00, false, false,
303 { V4L2_PIX_FMT_XRGB444, { 16, 0, 0 }, 1, 1, 1, 0x01, false, false,
307 { V4L2_PIX_FMT_XRGB555, { 16, 0, 0 }, 1, 1, 1, 0x04, false, false,
311 { V4L2_PIX_FMT_RGB565, { 16, 0, 0 }, 1, 1, 1, 0x06, false, false,
315 { V4L2_PIX_FMT_ABGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
318 { V4L2_PIX_FMT_XBGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
321 { V4L2_PIX_FMT_ARGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
325 { V4L2_PIX_FMT_XRGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
329 { V4L2_PIX_FMT_RGB24, { 24, 0, 0 }, 1, 1, 1, 0x15, false, false,
333 { V4L2_PIX_FMT_BGR24, { 24, 0, 0 }, 1, 1, 1, 0x18, false, false,
337 { V4L2_PIX_FMT_ARGB444, { 16, 0, 0 }, 1, 1, 1, 0x19, false, false,
341 { V4L2_PIX_FMT_ARGB555, { 16, 0, 0 }, 1, 1, 1, 0x1b, false, false,
348 { V4L2_PIX_FMT_NV16M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, false,
352 { V4L2_PIX_FMT_NV61M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, true,
356 { V4L2_PIX_FMT_NV12M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, false,
360 { V4L2_PIX_FMT_NV21M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, true,
364 { V4L2_PIX_FMT_UYVY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, false,
368 { V4L2_PIX_FMT_VYUY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, true,
372 { V4L2_PIX_FMT_YUYV, { 16, 0, 0 }, 1, 2, 1, 0x47, true, false,
376 { V4L2_PIX_FMT_YVYU, { 16, 0, 0 }, 1, 2, 1, 0x47, true, true,
380 { V4L2_PIX_FMT_YUV444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, false,
384 { V4L2_PIX_FMT_YVU444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, true,
388 { V4L2_PIX_FMT_YUV422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, false,
392 { V4L2_PIX_FMT_YVU422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, true,
396 { V4L2_PIX_FMT_YUV420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, false,
400 { V4L2_PIX_FMT_YVU420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, true,
408 return fmt->fmt <= 0x1b; /* Last RGB code */ in fdp1_fmt_is_rgb()
412 * FDP1 Lookup tables range from 0...255 only
418 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf,
419 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3,
420 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff,
424 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf,
425 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3,
426 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff,
430 0x80,
434 0x80,
438 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
439 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
440 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
441 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
442 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
443 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
444 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
445 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
446 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
447 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
448 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
449 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
450 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
451 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
452 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
453 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
454 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
455 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
456 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
457 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
458 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
459 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
460 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
461 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
462 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
463 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
464 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
465 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
466 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
467 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
468 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
469 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
487 for (i = 0; i < ARRAY_SIZE(fdp1_formats); i++) { in fdp1_find_format()
497 FDP1_PROGRESSIVE = 0, /* Must be zero when !deinterlacing */
608 * for supported formats. 0-255 only
691 memset(job, 0, sizeof(struct fdp1_job)); in fdp1_job_free()
781 dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg); in fdp1_read()
789 dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg); in fdp1_write()
855 for (i = 0; i < len; i++) in fdp1_write_lut()
909 smsk_addr = ctx->smsk_addr[0]; in fdp1_configure_rpf()
926 fdp1_write(fdp1, job->previous->addrs[0], FD1_RPF0_ADDR_Y); in fdp1_configure_rpf()
929 fdp1_write(fdp1, job->active->addrs[0], FD1_RPF1_ADDR_Y); in fdp1_configure_rpf()
935 fdp1_write(fdp1, job->next->addrs[0], FD1_RPF2_ADDR_Y); in fdp1_configure_rpf()
949 pstride = q_data->format.plane_fmt[0].bytesperline in fdp1_configure_wpf()
994 fdp1_write(fdp1, job->dst->addrs[0], FD1_WPF_ADDR_Y); in fdp1_configure_wpf()
1017 if (ctx->sequence == 0 || ctx->aborting) in fdp1_configure_deint_mode()
1035 if (!(ctx->sequence == 0 || ctx->aborting)) in fdp1_configure_deint_mode()
1083 return 0; in fdp1_device_process()
1126 return 0; in fdp1_device_process()
1154 return 0; in fdp1_m2m_job_ready()
1170 fdp1_write(ctx->fdp1, 0, FD1_CTL_SGCMD); in fdp1_m2m_job_abort()
1218 job->dst = &fbuf->fields[0]; in fdp1_prepare_job()
1272 ctx->translen = 0; in fdp1_m2m_device_run()
1278 for (i = 0; i < buf->num_fields; i++) { in fdp1_m2m_device_run()
1290 if (ctx->translen == 0) { in fdp1_m2m_device_run()
1347 ctx->num_processed = 0; in device_frame_end()
1368 return 0; in fdp1_vidioc_querycap()
1375 num = 0; in fdp1_enum_fmt()
1377 for (i = 0; i < ARRAY_SIZE(fdp1_formats); ++i) { in fdp1_enum_fmt()
1392 return 0; in fdp1_enum_fmt()
1418 return 0; in fdp1_g_fmt()
1427 for (i = 0; i < min_t(unsigned int, fmt->num_planes, 2U); ++i) { in fdp1_compute_stride()
1428 unsigned int hsub = i > 0 ? fmt->hsub : 1; in fdp1_compute_stride()
1429 unsigned int vsub = i > 0 ? fmt->vsub : 1; in fdp1_compute_stride()
1491 * Align the width and height for YUV 4:2:2 and 4:2:0 formats and clamp in fdp1_try_fmt_output()
1594 dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n", in fdp1_try_fmt()
1599 return 0; in fdp1_try_fmt()
1621 q_data->stride_y = pix->plane_fmt[0].bytesperline; in fdp1_set_format()
1641 memset(dst_data->format.plane_fmt, 0, in fdp1_set_format()
1651 dst_data->stride_y = dst_data->format.plane_fmt[0].bytesperline; in fdp1_set_format()
1669 dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n", in fdp1_s_fmt()
1674 return 0; in fdp1_s_fmt()
1689 return 0; in fdp1_g_ctrl()
1710 return 0; in fdp1_s_ctrl()
1774 return 0; in fdp1_queue_setup()
1779 for (i = 0; i < *nplanes; i++) in fdp1_queue_setup()
1782 return 0; in fdp1_queue_setup()
1799 for (i = 0; i < vbuf->vb2_buf.num_planes; ++i) in fdp1_buf_prepare_field()
1834 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) in fdp1_buf_prepare_field()
1836 (i == 0 ? q_data->stride_y : q_data->stride_c); in fdp1_buf_prepare_field()
1840 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) in fdp1_buf_prepare_field()
1842 (i == 0 ? q_data->stride_y : q_data->stride_c); in fdp1_buf_prepare_field()
1892 for (i = 0; i < q_data->format.num_planes; i++) { in fdp1_buf_prepare()
1908 for (i = 0; i < buf->num_fields; ++i) in fdp1_buf_prepare()
1911 return 0; in fdp1_buf_prepare()
1953 ctx->smsk_addr[0] = smsk_base; in fdp1_start_streaming()
1958 return 0; in fdp1_start_streaming()
1994 ctx->smsk_cpu, ctx->smsk_addr[0]); in fdp1_stop_streaming()
1995 ctx->smsk_addr[0] = ctx->smsk_addr[1] = 0; in fdp1_stop_streaming()
2081 int ret = 0; in fdp1_open()
2100 ctx->sequence = 0; in fdp1_open()
2107 FDP1_NEXTFIELD, BIT(0), FDP1_FIXED3D, in fdp1_open()
2116 V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 255); in fdp1_open()
2127 memset(&format, 0, sizeof(format)); in fdp1_open()
2139 if (ret < 0) in fdp1_open()
2148 return 0; in fdp1_open()
2177 return 0; in fdp1_release()
2223 dprintk(fdp1, "IRQ: 0x%x %s%s%s\n", int_status, in fdp1_irq_handler()
2232 "Control Status = 0x%08x : VINT_CNT = %d %s:%s:%s:%s\n", in fdp1_irq_handler()
2274 for (i = 0; i < ARRAY_SIZE(fdp1->jobs); i++) in fdp1_probe()
2285 fdp1->regs = devm_platform_ioremap_resource(pdev, 0); in fdp1_probe()
2290 ret = platform_get_irq(pdev, 0); in fdp1_probe()
2291 if (ret < 0) in fdp1_probe()
2295 ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0, in fdp1_probe()
2303 fcp_node = of_parse_phandle(pdev->dev.of_node, "renesas,fcp", 0); in fdp1_probe()
2347 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); in fdp1_probe()
2359 if (ret < 0) in fdp1_probe()
2380 dev_err(fdp1->dev, "FDP1 Unidentifiable (0x%08x)\n", in fdp1_probe()
2387 return 0; in fdp1_probe()
2420 return 0; in fdp1_pm_runtime_suspend()