424 				 u8 vfe, u8 enable)  in ispif_select_clk_mux()  argument
431 		val &= ~(0xf << (vfe * 8));  in ispif_select_clk_mux()
433 			val |= (csid << (vfe * 8));  in ispif_select_clk_mux()
439 		val &= ~(0xf << (vfe * 12));  in ispif_select_clk_mux()
441 			val |= (csid << (vfe * 12));  in ispif_select_clk_mux()
447 		val &= ~(0xf << (4 + (vfe * 8)));  in ispif_select_clk_mux()
449 			val |= (csid << (4 + (vfe * 8)));  in ispif_select_clk_mux()
455 		val &= ~(0xf << (4 + (vfe * 12)));  in ispif_select_clk_mux()
457 			val |= (csid << (4 + (vfe * 12)));  in ispif_select_clk_mux()
463 		val &= ~(0xf << (8 + (vfe * 12)));  in ispif_select_clk_mux()
465 			val |= (csid << (8 + (vfe * 12)));  in ispif_select_clk_mux()
482 				      enum ispif_intf intf, u8 vfe)  in ispif_validate_intf_status()  argument
490 			ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));  in ispif_validate_intf_status()
494 			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));  in ispif_validate_intf_status()
498 			ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));  in ispif_validate_intf_status()
502 			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));  in ispif_validate_intf_status()
506 			ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));  in ispif_validate_intf_status()
528 			       enum ispif_intf intf, u8 vfe)  in ispif_wait_for_stop()  argument
536 		addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);  in ispif_wait_for_stop()
539 		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);  in ispif_wait_for_stop()
542 		addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);  in ispif_wait_for_stop()
545 		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);  in ispif_wait_for_stop()
548 		addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);  in ispif_wait_for_stop()
573 			      u8 csid, u8 vfe, u8 enable)  in ispif_select_csid()  argument
577 	val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));  in ispif_select_csid()
606 	writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));  in ispif_select_csid()
618 			     u8 cid, u8 vfe, u8 enable)  in ispif_select_cid()  argument
626 		addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);  in ispif_select_cid()
629 		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);  in ispif_select_cid()
632 		addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);  in ispif_select_cid()
635 		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);  in ispif_select_cid()
638 		addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);  in ispif_select_cid()
659 			     u8 vfe, u8 enable)  in ispif_config_irq()  argument
665 		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));  in ispif_config_irq()
669 		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));  in ispif_config_irq()
671 			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));  in ispif_config_irq()
674 		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));  in ispif_config_irq()
678 		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));  in ispif_config_irq()
680 			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));  in ispif_config_irq()
683 		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));  in ispif_config_irq()
687 		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));  in ispif_config_irq()
689 			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));  in ispif_config_irq()
692 		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));  in ispif_config_irq()
696 		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));  in ispif_config_irq()
698 			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));  in ispif_config_irq()
701 		val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));  in ispif_config_irq()
705 		writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));  in ispif_config_irq()
707 			       ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));  in ispif_config_irq()
724 			      enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)  in ispif_config_pack()  argument
735 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);  in ispif_config_pack()
737 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);  in ispif_config_pack()
741 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);  in ispif_config_pack()
743 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);  in ispif_config_pack()
747 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);  in ispif_config_pack()
749 			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);  in ispif_config_pack()
772 			       enum ispif_intf intf, u8 vfe, u8 vc)  in ispif_set_intf_cmd()  argument
777 		val = &ispif->intf_cmd[vfe].cmd_1;  in ispif_set_intf_cmd()
781 		writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));  in ispif_set_intf_cmd()
784 		val = &ispif->intf_cmd[vfe].cmd_0;  in ispif_set_intf_cmd()
788 		writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));  in ispif_set_intf_cmd()
809 	u8 vfe = line->vfe_id;  in ispif_set_stream()  local
821 		ispif_select_clk_mux(ispif, intf, csid, vfe, 1);  in ispif_set_stream()
823 		ret = ispif_validate_intf_status(ispif, intf, vfe);  in ispif_set_stream()
829 		ispif_select_csid(ispif, intf, csid, vfe, 1);  in ispif_set_stream()
830 		ispif_select_cid(ispif, intf, cid, vfe, 1);  in ispif_set_stream()
831 		ispif_config_irq(ispif, intf, vfe, 1);  in ispif_set_stream()
836 					  intf, cid, vfe, 1);  in ispif_set_stream()
838 				   intf, vfe, vc);  in ispif_set_stream()
842 				   intf, vfe, vc);  in ispif_set_stream()
845 		ret = ispif_wait_for_stop(ispif, intf, vfe);  in ispif_set_stream()
854 					  intf, cid, vfe, 0);  in ispif_set_stream()
855 		ispif_config_irq(ispif, intf, vfe, 0);  in ispif_set_stream()
856 		ispif_select_cid(ispif, intf, cid, vfe, 0);  in ispif_set_stream()
857 		ispif_select_csid(ispif, intf, csid, vfe, 0);  in ispif_set_stream()
858 		ispif_select_clk_mux(ispif, intf, csid, vfe, 0);  in ispif_set_stream()
1263 	struct vfe_device *vfe;  in ispif_get_vfe_id()  local
1267 	vfe = to_vfe(line);  in ispif_get_vfe_id()
1269 	*id = vfe->id;  in ispif_get_vfe_id()