25 #define CSID_HW_VERSION		0x0
26 #define		HW_VERSION_STEPPING	0
30 #define CSID_RST_STROBES	0x10
31 #define		RST_STROBES	0
33 #define CSID_CSI2_RX_IRQ_STATUS	0x20
34 #define	CSID_CSI2_RX_IRQ_MASK	0x24
35 #define CSID_CSI2_RX_IRQ_CLEAR	0x28
37 #define CSID_CSI2_RDIN_IRQ_STATUS(rdi)		((csid_is_lite(csid) ? 0x30 : 0x40) \
38 						 + 0x10 * (rdi))
39 #define CSID_CSI2_RDIN_IRQ_MASK(rdi)		((csid_is_lite(csid) ? 0x34 : 0x44) \
40 						 + 0x10 * (rdi))
41 #define CSID_CSI2_RDIN_IRQ_CLEAR(rdi)		((csid_is_lite(csid) ? 0x38 : 0x48) \
42 						 + 0x10 * (rdi))
43 #define CSID_CSI2_RDIN_IRQ_SET(rdi)		((csid_is_lite(csid) ? 0x3C : 0x4C) \
44 						 + 0x10 * (rdi))
46 #define CSID_TOP_IRQ_STATUS	0x70
47 #define		TOP_IRQ_STATUS_RESET_DONE 0
48 #define CSID_TOP_IRQ_MASK	0x74
49 #define CSID_TOP_IRQ_CLEAR	0x78
50 #define CSID_TOP_IRQ_SET	0x7C
51 #define CSID_IRQ_CMD		0x80
52 #define		IRQ_CMD_CLEAR	0
55 #define CSID_CSI2_RX_CFG0	0x100
56 #define		CSI2_RX_CFG0_NUM_ACTIVE_LANES	0
64 #define CSID_CSI2_RX_CFG1	0x104
65 #define		CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN		0
72 #define			CGC_MODE_DYNAMIC_GATING		0
75 #define CSID_RDI_CFG0(rdi)			((csid_is_lite(csid) ? 0x200 : 0x300) \
76 						 + 0x100 * (rdi))
77 #define		RDI_CFG0_BYTE_CNTR_EN		0
86 #define			CGC_MODE_DYNAMIC	0
89 #define			PLAIN_ALIGNMENT_LSB	0
100 #define CSID_RDI_CFG1(rdi)			((csid_is_lite(csid) ? 0x204 : 0x304)\
101 						+ 0x100 * (rdi))
102 #define		RDI_CFG1_TIMESTAMP_STB_SEL	0
104 #define CSID_RDI_CTRL(rdi)			((csid_is_lite(csid) ? 0x208 : 0x308)\
105 						+ 0x100 * (rdi))
106 #define		RDI_CTRL_HALT_CMD		0
107 #define			HALT_CMD_HALT_AT_FRAME_BOUNDARY		0
111 #define CSID_RDI_FRM_DROP_PATTERN(rdi)			((csid_is_lite(csid) ? 0x20C : 0x30C)\
112 							+ 0x100 * (rdi))
113 #define CSID_RDI_FRM_DROP_PERIOD(rdi)			((csid_is_lite(csid) ? 0x210 : 0x310)\
114 							+ 0x100 * (rdi))
115 #define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi)		((csid_is_lite(csid) ? 0x214 : 0x314)\
116 							+ 0x100 * (rdi))
117 #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi)		((csid_is_lite(csid) ? 0x218 : 0x318)\
118 							+ 0x100 * (rdi))
119 #define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi)		((csid_is_lite(csid) ? 0x224 : 0x324)\
120 							+ 0x100 * (rdi))
121 #define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi)		((csid_is_lite(csid) ? 0x228 : 0x328)\
122 							+ 0x100 * (rdi))
123 #define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi)		((csid_is_lite(csid) ? 0x22C : 0x32C)\
124 							+ 0x100 * (rdi))
125 #define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi)		((csid_is_lite(csid) ? 0x230 : 0x330)\
126 							+ 0x100 * (rdi))
128 #define CSID_TPG_CTRL		0x600
129 #define		TPG_CTRL_TEST_EN		0
136 #define CSID_TPG_VC_CFG0	0x604
137 #define		TPG_VC_CFG0_VC_NUM			0
139 #define			NUM_ACTIVE_SLOTS_0_ENABLED	0
144 #define			INTELEAVING_MODE_INTERLEAVED	0
148 #define CSID_TPG_VC_CFG1	0x608
149 #define		TPG_VC_CFG1_H_BLANKING_COUNT		0
153 #define CSID_TPG_LFSR_SEED	0x60C
155 #define CSID_TPG_DT_n_CFG_0(n)	(0x610 + (n) * 0xC)
156 #define		TPG_DT_n_CFG_0_FRAME_HEIGHT	0
159 #define CSID_TPG_DT_n_CFG_1(n)	(0x614 + (n) * 0xC)
160 #define		TPG_DT_n_CFG_1_DATA_TYPE	0
164 #define CSID_TPG_DT_n_CFG_2(n)	(0x618 + (n) * 0xC)
165 #define		TPG_DT_n_CFG_2_PAYLOAD_MODE		0
169 #define CSID_TPG_COLOR_BARS_CFG	0x640
170 #define		TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN	0
175 #define CSID_TPG_COLOR_BOX_CFG	0x644
176 #define		TPG_COLOR_BOX_CFG_MODE		0
227 	val |= 0 << TPG_VC_CFG0_NUM_FRAMES;  in __csid_configure_testgen()
230 	val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;  in __csid_configure_testgen()
231 	val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;  in __csid_configure_testgen()
234 	writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);  in __csid_configure_testgen()
236 	val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;  in __csid_configure_testgen()
237 	val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;  in __csid_configure_testgen()
238 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));  in __csid_configure_testgen()
241 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));  in __csid_configure_testgen()
244 	val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;  in __csid_configure_testgen()
246 	writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));  in __csid_configure_testgen()
248 	writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);  in __csid_configure_testgen()
250 	writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);  in __csid_configure_testgen()
256 	val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;  in __csid_configure_testgen()
257 	val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;  in __csid_configure_testgen()
280 	 * CID   : VC 3:0 << 2 | DT_ID 1:0  in __csid_configure_rdi_stream()
282 	u8 dt_id = vc & 0x03;  in __csid_configure_rdi_stream()
301 	val = 0;  in __csid_configure_rdi_stream()
307 	val = 0;  in __csid_configure_rdi_stream()
313 	val = 0;  in __csid_configure_rdi_stream()
319 	val = 0;  in __csid_configure_rdi_stream()
322 	val = 0;  in __csid_configure_rdi_stream()
335 	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)  in csid_configure_stream()
348 	if (val > 0 && val <= csid->testgen.nmodes)  in csid_configure_testgen_pattern()
351 	return 0;  in csid_configure_testgen_pattern()
368 	hw_gen = (hw_version >> HW_VERSION_GENERATION) & 0xF;  in csid_hw_version()
369 	hw_rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF;  in csid_hw_version()
370 	hw_step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF;  in csid_hw_version()
399 	for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)  in csid_isr()
418  * Return 0 on success or a negative error code otherwise
433 	val = 0x1e << RST_STROBES;  in csid_reset()
443 	return 0;  in csid_reset()
471 		if (match_format_idx > 0)  in csid_src_pad_code()
472 			return 0;  in csid_src_pad_code()