Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
14 #define CHNL_CTRL_CHNL_EN BIT(31)
15 #define CHNL_CTRL_CLK_EN BIT(30)
16 #define CHNL_CTRL_CHNL_BYPASS BIT(29)
21 #define CHNL_CTRL_SW_RST BIT(24)
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
27 #define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
87 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)
88 #define CHNL_IMG_CTRL_GBL_ALPHA_EN BIT(15)
101 #define CHNL_IMG_CTRL_CROP_EN BIT(7)
102 #define CHNL_IMG_CTRL_VFLIP_EN BIT(6)
103 #define CHNL_IMG_CTRL_HFLIP_EN BIT(5)
104 #define CHNL_IMG_CTRL_YCBCR_MODE BIT(3)
111 #define CHNL_IMG_CTRL_CSC_BYPASS BIT(0)
115 #define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR BIT(15)
116 #define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR BIT(14)
138 #define CHNL_IMG_CFG_HEIGHT(n) ((n) << 16)
139 #define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
145 #define CHNL_IER_MEM_RD_DONE_EN BIT(31)
146 #define CHNL_IER_LINE_RCVD_EN BIT(30)
147 #define CHNL_IER_FRM_RCVD_EN BIT(29)
148 #define CHNL_IER_AXI_WR_ERR_V_EN BIT(28)
149 #define CHNL_IER_AXI_WR_ERR_U_EN BIT(27)
150 #define CHNL_IER_AXI_WR_ERR_Y_EN BIT(26)
151 #define CHNL_IER_AXI_RD_ERR_EN BIT(25)
155 #define CHNL_STS_MEM_RD_DONE BIT(31)
156 #define CHNL_STS_LINE_STRD BIT(30)
157 #define CHNL_STS_FRM_STRD BIT(29)
158 #define CHNL_STS_AXI_WR_ERR_V BIT(28)
159 #define CHNL_STS_AXI_WR_ERR_U BIT(27)
160 #define CHNL_STS_AXI_WR_ERR_Y BIT(26)
161 #define CHNL_STS_AXI_RD_ERR BIT(25)
162 #define CHNL_STS_OFLW_PANIC_V_BUF BIT(24)
163 #define CHNL_STS_EXCS_OFLW_V_BUF BIT(23)
164 #define CHNL_STS_OFLW_V_BUF BIT(22)
165 #define CHNL_STS_OFLW_PANIC_U_BUF BIT(21)
166 #define CHNL_STS_EXCS_OFLW_U_BUF BIT(20)
167 #define CHNL_STS_OFLW_U_BUF BIT(19)
168 #define CHNL_STS_OFLW_PANIC_Y_BUF BIT(18)
169 #define CHNL_STS_EXCS_OFLW_Y_BUF BIT(17)
170 #define CHNL_STS_OFLW_Y_BUF BIT(16)
171 #define CHNL_STS_EARLY_VSYNC_ERR BIT(15)
172 #define CHNL_STS_LATE_VSYNC_ERR BIT(14)
173 #define CHNL_STS_MEM_RD_OFLOW BIT(10)
174 #define CHNL_STS_BUF2_ACTIVE BIT(9)
175 #define CHNL_STS_BUF1_ACTIVE BIT(8)
181 #define CHNL_SCALE_FACTOR_Y_SCALE(n) ((n) << 16)
182 #define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16)
188 #define CHNL_SCALE_OFFSET_Y_SCALE(n) ((n) << 16)
189 #define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)
195 #define CHNL_CROP_ULC_X(n) ((n) << 16)
196 #define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)
202 #define CHNL_CROP_LRC_X(n) ((n) << 16)
203 #define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)
209 #define CHNL_CSC_COEFF0_A2(n) ((n) << 16)
210 #define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16)
216 #define CHNL_CSC_COEFF1_B1(n) ((n) << 16)
217 #define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16)
223 #define CHNL_CSC_COEFF2_B3(n) ((n) << 16)
224 #define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16)
230 #define CHNL_CSC_COEFF3_C2(n) ((n) << 16)
231 #define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16)
237 #define CHNL_CSC_COEFF4_D1(n) ((n) << 16)
238 #define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16)
244 #define CHNL_CSC_COEFF5_D3(n) ((n) << 16)
245 #define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16)
253 #define CHNL_ROI_0_ALPHA_EN BIT(16)
257 #define CHNL_ROI_0_ULC_X(n) ((n) << 16)
258 #define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)
264 #define CHNL_ROI_0_LRC_X(n) ((n) << 16)
265 #define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)
273 #define CHNL_ROI_1_ALPHA_EN BIT(16)
277 #define CHNL_ROI_1_ULC_X(n) ((n) << 16)
278 #define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)
284 #define CHNL_ROI_1_LRC_X(n) ((n) << 16)
285 #define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)
293 #define CHNL_ROI_2_ALPHA_EN BIT(16)
297 #define CHNL_ROI_2_ULC_X(n) ((n) << 16)
298 #define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)
304 #define CHNL_ROI_2_LRC_X(n) ((n) << 16)
305 #define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16)
313 #define CHNL_ROI_3_ALPHA_EN BIT(16)
317 #define CHNL_ROI_3_ULC_X(n) ((n) << 16)
318 #define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16)
324 #define CHNL_ROI_3_LRC_X(n) ((n) << 16)
325 #define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16)
347 #define CHNL_IN_BUF_PITCH_FRM_PITCH(n) ((n) << 16)
348 #define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16)
372 #define CHNL_MEM_RD_CTRL_READ_MEM BIT(0)
385 #define CHNL_SCL_IMG_CFG_HEIGHT(n) ((n) << 16)
386 #define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
394 #define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16)
397 /* Channel Output Y-Buffer 1 Extended Address Bits */
400 /* Channel Output U-Buffer 1 Extended Address Bits */
403 /* Channel Output V-Buffer 1 Extended Address Bits */
406 /* Channel Output Y-Buffer 2 Extended Address Bits */
409 /* Channel Output U-Buffer 2 Extended Address Bits */
412 /* Channel Output V-Buffer 2 Extended Address Bits */