Lines Matching refs:tegra_vde_writel
65 tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
66 tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
76 tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23), in tegra_vde_setup_mbe_frame_idx()
78 tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23), in tegra_vde_setup_mbe_frame_idx()
88 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
103 tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), in tegra_vde_mbe_set_0xa_reg()
105 tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), in tegra_vde_mbe_set_0xa_reg()
145 tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); in tegra_vde_push_to_bsev_icmdqueue()
161 tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4); in tegra_vde_setup_frameid()
162 tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4); in tegra_vde_setup_frameid()
163 tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4); in tegra_vde_setup_frameid()
164 tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4); in tegra_vde_setup_frameid()
165 tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); in tegra_vde_setup_frameid()
287 tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C); in tegra_vde_setup_hw_context()
288 tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00); in tegra_vde_setup_hw_context()
289 tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04); in tegra_vde_setup_hw_context()
290 tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200); in tegra_vde_setup_hw_context()
291 tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04); in tegra_vde_setup_hw_context()
292 tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); in tegra_vde_setup_hw_context()
293 tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); in tegra_vde_setup_hw_context()
294 tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); in tegra_vde_setup_hw_context()
295 tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); in tegra_vde_setup_hw_context()
296 tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); in tegra_vde_setup_hw_context()
297 tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10); in tegra_vde_setup_hw_context()
298 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
299 tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); in tegra_vde_setup_hw_context()
300 tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); in tegra_vde_setup_hw_context()
301 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); in tegra_vde_setup_hw_context()
302 tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); in tegra_vde_setup_hw_context()
319 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); in tegra_vde_setup_hw_context()
320 tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size, in tegra_vde_setup_hw_context()
327 tegra_vde_writel(vde, value, vde->bsev, 0x88); in tegra_vde_setup_hw_context()
362 tegra_vde_writel(vde, value, vde->sxe, 0x10); in tegra_vde_setup_hw_context()
370 tegra_vde_writel(vde, value, vde->sxe, 0x40); in tegra_vde_setup_hw_context()
376 tegra_vde_writel(vde, value, vde->sxe, 0x44); in tegra_vde_setup_hw_context()
383 tegra_vde_writel(vde, value, vde->sxe, 0x48); in tegra_vde_setup_hw_context()
388 tegra_vde_writel(vde, value, vde->sxe, 0x4C); in tegra_vde_setup_hw_context()
393 tegra_vde_writel(vde, value, vde->sxe, 0x68); in tegra_vde_setup_hw_context()
395 tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); in tegra_vde_setup_hw_context()
398 tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c); in tegra_vde_setup_hw_context()
404 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
411 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
413 tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
414 tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
415 tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
420 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
442 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
458 tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); in tegra_vde_decode_frame()
459 tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1), in tegra_vde_decode_frame()