Lines Matching +full:gain +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
21 #include <linux/atmel-isc-media.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-image-sizes.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
30 #include <media/videobuf2-dma-contig.h>
32 #include "microchip-isc-regs.h"
33 #include "microchip-isc.h"
44 struct isc_ctrls *ctrls = &isc->ctrls; in isc_update_v4l2_ctrls()
47 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]); in isc_update_v4l2_ctrls()
48 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]); in isc_update_v4l2_ctrls()
49 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]); in isc_update_v4l2_ctrls()
50 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]); in isc_update_v4l2_ctrls()
52 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]); in isc_update_v4l2_ctrls()
53 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]); in isc_update_v4l2_ctrls()
54 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]); in isc_update_v4l2_ctrls()
55 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]); in isc_update_v4l2_ctrls()
60 struct isc_ctrls *ctrls = &isc->ctrls; in isc_update_awb_ctrls()
64 regmap_write(isc->regmap, ISC_WB_O_RGR, in isc_update_awb_ctrls()
65 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | in isc_update_awb_ctrls()
66 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); in isc_update_awb_ctrls()
67 regmap_write(isc->regmap, ISC_WB_O_BGB, in isc_update_awb_ctrls()
68 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | in isc_update_awb_ctrls()
69 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); in isc_update_awb_ctrls()
70 regmap_write(isc->regmap, ISC_WB_G_RGR, in isc_update_awb_ctrls()
71 ctrls->gain[ISC_HIS_CFG_MODE_R] | in isc_update_awb_ctrls()
72 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); in isc_update_awb_ctrls()
73 regmap_write(isc->regmap, ISC_WB_G_BGB, in isc_update_awb_ctrls()
74 ctrls->gain[ISC_HIS_CFG_MODE_B] | in isc_update_awb_ctrls()
75 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); in isc_update_awb_ctrls()
84 isc->ctrls.gain[c] = 1 << 9; in isc_reset_awb_ctrls()
86 isc->ctrls.offset[c] = 0; in isc_reset_awb_ctrls()
95 unsigned int size = isc->fmt.fmt.pix.sizeimage; in isc_queue_setup()
98 return sizes[0] < size ? -EINVAL : 0; in isc_queue_setup()
109 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); in isc_buffer_prepare()
110 unsigned long size = isc->fmt.fmt.pix.sizeimage; in isc_buffer_prepare()
113 dev_err(isc->dev, "buffer too small (%lu < %lu)\n", in isc_buffer_prepare()
115 return -EINVAL; in isc_buffer_prepare()
120 vbuf->field = isc->fmt.fmt.pix.field; in isc_buffer_prepare()
127 struct regmap *regmap = isc->regmap; in isc_crop_pfe()
130 h = isc->fmt.fmt.pix.height; in isc_crop_pfe()
131 w = isc->fmt.fmt.pix.width; in isc_crop_pfe()
134 * In case the sensor is not RAW, it will output a pixel (12-16 bits) in isc_crop_pfe()
135 * with two samples on the ISC Data bus (which is 8-12) in isc_crop_pfe()
139 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) { in isc_crop_pfe()
153 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK)); in isc_crop_pfe()
157 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK)); in isc_crop_pfe()
166 struct regmap *regmap = isc->regmap; in isc_start_dma()
167 u32 sizeimage = isc->fmt.fmt.pix.sizeimage; in isc_start_dma()
171 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); in isc_start_dma()
172 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); in isc_start_dma()
174 switch (isc->config.fourcc) { in isc_start_dma()
176 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, in isc_start_dma()
178 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, in isc_start_dma()
182 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, in isc_start_dma()
184 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, in isc_start_dma()
191 dctrl_dview = isc->config.dctrl_dview; in isc_start_dma()
193 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, in isc_start_dma()
195 spin_lock(&isc->awb_lock); in isc_start_dma()
197 spin_unlock(&isc->awb_lock); in isc_start_dma()
202 struct regmap *regmap = isc->regmap; in isc_set_pipeline()
203 struct isc_ctrls *ctrls = &isc->ctrls; in isc_set_pipeline()
208 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ in isc_set_pipeline()
211 regmap_field_write(isc->pipeline[i], val); in isc_set_pipeline()
217 bay_cfg = isc->config.sd_format->cfa_baycfg; in isc_set_pipeline()
225 gamma = &isc->gamma_table[ctrls->gamma_index][0]; in isc_set_pipeline()
230 isc->config_dpc(isc); in isc_set_pipeline()
231 isc->config_csc(isc); in isc_set_pipeline()
232 isc->config_cbc(isc); in isc_set_pipeline()
233 isc->config_cc(isc); in isc_set_pipeline()
234 isc->config_gam(isc); in isc_set_pipeline()
239 struct regmap *regmap = isc->regmap; in isc_update_profile()
246 while ((sr & ISC_CTRL_UPPRO) && counter--) { in isc_update_profile()
252 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n"); in isc_update_profile()
253 return -ETIMEDOUT; in isc_update_profile()
261 struct regmap *regmap = isc->regmap; in isc_set_histogram()
262 struct isc_ctrls *ctrls = &isc->ctrls; in isc_set_histogram()
265 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, in isc_set_histogram()
267 (isc->config.sd_format->cfa_baycfg in isc_set_histogram()
270 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, in isc_set_histogram()
273 ctrls->hist_id = ISC_HIS_CFG_MODE_GR; in isc_set_histogram()
277 ctrls->hist_stat = HIST_ENABLED; in isc_set_histogram()
280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, in isc_set_histogram()
283 ctrls->hist_stat = HIST_DISABLED; in isc_set_histogram()
289 struct regmap *regmap = isc->regmap; in isc_configure()
291 struct isc_subdev_entity *subdev = isc->current_subdev; in isc_configure()
293 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; in isc_configure()
294 pipeline = isc->config.bits_pipeline; in isc_configure()
296 dcfg = isc->config.dcfg_imode | isc->dcfg; in isc_configure()
298 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; in isc_configure()
306 isc->config_rlp(isc); in isc_configure()
308 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); in isc_configure()
317 if (isc->ctrls.awb && in isc_configure()
318 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_configure()
331 return media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe); in isc_prepare_streaming()
337 struct regmap *regmap = isc->regmap; in isc_start_streaming()
343 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1); in isc_start_streaming()
344 if (ret && ret != -ENOIOCTLCMD) { in isc_start_streaming()
345 dev_err(isc->dev, "stream on failed in subdev %d\n", ret); in isc_start_streaming()
349 ret = pm_runtime_resume_and_get(isc->dev); in isc_start_streaming()
351 dev_err(isc->dev, "RPM resume failed in subdev %d\n", in isc_start_streaming()
363 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_start_streaming()
365 isc->sequence = 0; in isc_start_streaming()
366 isc->stop = false; in isc_start_streaming()
367 reinit_completion(&isc->comp); in isc_start_streaming()
369 isc->cur_frm = list_first_entry(&isc->dma_queue, in isc_start_streaming()
371 list_del(&isc->cur_frm->list); in isc_start_streaming()
376 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_start_streaming()
378 /* if we streaming from RAW, we can do one-shot white balance adj */ in isc_start_streaming()
379 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_start_streaming()
380 v4l2_ctrl_activate(isc->do_wb_ctrl, true); in isc_start_streaming()
385 pm_runtime_put_sync(isc->dev); in isc_start_streaming()
387 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); in isc_start_streaming()
390 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_start_streaming()
391 list_for_each_entry(buf, &isc->dma_queue, list) in isc_start_streaming()
392 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); in isc_start_streaming()
393 INIT_LIST_HEAD(&isc->dma_queue); in isc_start_streaming()
394 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_start_streaming()
404 media_pipeline_stop(isc->video_dev.entity.pads); in isc_unprepare_streaming()
414 mutex_lock(&isc->awb_mutex); in isc_stop_streaming()
415 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_stop_streaming()
417 isc->stop = true; in isc_stop_streaming()
420 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) in isc_stop_streaming()
421 dev_err(isc->dev, "Timeout waiting for end of the capture\n"); in isc_stop_streaming()
423 mutex_unlock(&isc->awb_mutex); in isc_stop_streaming()
426 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); in isc_stop_streaming()
428 pm_runtime_put_sync(isc->dev); in isc_stop_streaming()
431 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); in isc_stop_streaming()
432 if (ret && ret != -ENOIOCTLCMD) in isc_stop_streaming()
433 dev_err(isc->dev, "stream off failed in subdev\n"); in isc_stop_streaming()
436 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_stop_streaming()
437 if (unlikely(isc->cur_frm)) { in isc_stop_streaming()
438 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf, in isc_stop_streaming()
440 isc->cur_frm = NULL; in isc_stop_streaming()
442 list_for_each_entry(buf, &isc->dma_queue, list) in isc_stop_streaming()
443 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); in isc_stop_streaming()
444 INIT_LIST_HEAD(&isc->dma_queue); in isc_stop_streaming()
445 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_stop_streaming()
452 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); in isc_buffer_queue()
455 spin_lock_irqsave(&isc->dma_queue_lock, flags); in isc_buffer_queue()
456 if (!isc->cur_frm && list_empty(&isc->dma_queue) && in isc_buffer_queue()
457 vb2_start_streaming_called(vb->vb2_queue)) { in isc_buffer_queue()
458 isc->cur_frm = buf; in isc_buffer_queue()
461 list_add_tail(&buf->list, &isc->dma_queue); in isc_buffer_queue()
463 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); in isc_buffer_queue()
481 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); in isc_querycap()
482 strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card)); in isc_querycap()
491 u32 index = f->index; in isc_enum_fmt_vid_cap()
499 if (!f->mbus_code) { in isc_enum_fmt_vid_cap()
500 if (index >= isc->controller_formats_size) in isc_enum_fmt_vid_cap()
501 return -EINVAL; in isc_enum_fmt_vid_cap()
503 f->pixelformat = isc->controller_formats[index].fourcc; in isc_enum_fmt_vid_cap()
516 fmt = isc_find_format_by_code(isc, f->mbus_code, &i); in isc_enum_fmt_vid_cap()
518 return -EINVAL; in isc_enum_fmt_vid_cap()
521 f->pixelformat = fmt->fourcc; in isc_enum_fmt_vid_cap()
529 if (!ISC_IS_FORMAT_RAW(f->mbus_code)) in isc_enum_fmt_vid_cap()
530 return -EINVAL; in isc_enum_fmt_vid_cap()
536 * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc. in isc_enum_fmt_vid_cap()
538 for (i = 0; i < isc->controller_formats_size; i++) { in isc_enum_fmt_vid_cap()
539 if (isc->controller_formats[i].raw) in isc_enum_fmt_vid_cap()
542 f->pixelformat = isc->controller_formats[i].fourcc; in isc_enum_fmt_vid_cap()
548 return -EINVAL; in isc_enum_fmt_vid_cap()
556 *fmt = isc->fmt; in isc_g_fmt_vid_cap()
571 switch (isc->try_config.fourcc) { in isc_try_validate_formats()
613 dev_err(isc->dev, "Requested unsupported format.\n"); in isc_try_validate_formats()
614 ret = -EINVAL; in isc_try_validate_formats()
616 dev_dbg(isc->dev, in isc_try_validate_formats()
621 !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_validate_formats()
622 dev_err(isc->dev, "Cannot output RAW if we do not receive RAW.\n"); in isc_try_validate_formats()
623 return -EINVAL; in isc_try_validate_formats()
626 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) && in isc_try_validate_formats()
627 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { in isc_try_validate_formats()
628 dev_err(isc->dev, "Cannot output GREY if we do not receive RAW/GREY.\n"); in isc_try_validate_formats()
629 return -EINVAL; in isc_try_validate_formats()
633 ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { in isc_try_validate_formats()
634 dev_err(isc->dev, "Cannot convert GREY to another format.\n"); in isc_try_validate_formats()
635 return -EINVAL; in isc_try_validate_formats()
648 isc->try_config.rlp_cfg_mode = 0; in isc_try_configure_rlp_dma()
650 switch (isc->try_config.fourcc) { in isc_try_configure_rlp_dma()
655 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; in isc_try_configure_rlp_dma()
656 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
657 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
658 isc->try_config.bpp = 8; in isc_try_configure_rlp_dma()
659 isc->try_config.bpp_v4l2 = 8; in isc_try_configure_rlp_dma()
665 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10; in isc_try_configure_rlp_dma()
666 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
667 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
668 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
669 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
675 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12; in isc_try_configure_rlp_dma()
676 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
677 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
678 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
679 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
682 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; in isc_try_configure_rlp_dma()
683 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
684 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
685 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
686 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
689 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; in isc_try_configure_rlp_dma()
690 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
691 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
692 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
693 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
696 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; in isc_try_configure_rlp_dma()
697 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
698 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
699 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
700 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
704 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32; in isc_try_configure_rlp_dma()
705 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
706 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
707 isc->try_config.bpp = 32; in isc_try_configure_rlp_dma()
708 isc->try_config.bpp_v4l2 = 32; in isc_try_configure_rlp_dma()
711 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; in isc_try_configure_rlp_dma()
712 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; in isc_try_configure_rlp_dma()
713 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; in isc_try_configure_rlp_dma()
714 isc->try_config.bpp = 12; in isc_try_configure_rlp_dma()
715 isc->try_config.bpp_v4l2 = 8; /* only first plane */ in isc_try_configure_rlp_dma()
718 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; in isc_try_configure_rlp_dma()
719 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; in isc_try_configure_rlp_dma()
720 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; in isc_try_configure_rlp_dma()
721 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
722 isc->try_config.bpp_v4l2 = 8; /* only first plane */ in isc_try_configure_rlp_dma()
725 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; in isc_try_configure_rlp_dma()
726 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
727 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
728 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
729 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
732 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; in isc_try_configure_rlp_dma()
733 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
734 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
735 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
736 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
739 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; in isc_try_configure_rlp_dma()
740 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; in isc_try_configure_rlp_dma()
741 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
742 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
743 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
746 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; in isc_try_configure_rlp_dma()
747 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
748 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
749 isc->try_config.bpp = 8; in isc_try_configure_rlp_dma()
750 isc->try_config.bpp_v4l2 = 8; in isc_try_configure_rlp_dma()
753 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; in isc_try_configure_rlp_dma()
756 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; in isc_try_configure_rlp_dma()
757 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; in isc_try_configure_rlp_dma()
758 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
759 isc->try_config.bpp = 16; in isc_try_configure_rlp_dma()
760 isc->try_config.bpp_v4l2 = 16; in isc_try_configure_rlp_dma()
763 return -EINVAL; in isc_try_configure_rlp_dma()
767 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; in isc_try_configure_rlp_dma()
768 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; in isc_try_configure_rlp_dma()
769 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; in isc_try_configure_rlp_dma()
782 switch (isc->try_config.fourcc) { in isc_try_configure_pipeline()
789 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
790 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
794 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
799 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
800 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
805 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
810 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
811 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
815 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
822 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
823 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
827 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
833 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { in isc_try_configure_pipeline()
834 isc->try_config.bits_pipeline = CFA_ENABLE | in isc_try_configure_pipeline()
838 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
842 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) in isc_try_configure_pipeline()
843 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; in isc_try_configure_pipeline()
845 isc->try_config.bits_pipeline = 0x0; in isc_try_configure_pipeline()
849 isc->adapt_pipeline(isc); in isc_try_configure_pipeline()
856 struct v4l2_pix_format *pixfmt = &f->fmt.pix; in isc_try_fmt()
859 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) in isc_try_fmt()
860 return -EINVAL; in isc_try_fmt()
862 isc->try_config.fourcc = isc->controller_formats[0].fourcc; in isc_try_fmt()
865 for (i = 0; i < isc->controller_formats_size; i++) in isc_try_fmt()
866 if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) { in isc_try_fmt()
867 isc->try_config.fourcc = pixfmt->pixelformat; in isc_try_fmt()
874 v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0, in isc_try_fmt()
875 &pixfmt->height, 16, isc->max_height, 0, 0); in isc_try_fmt()
877 pixfmt->pixelformat = isc->try_config.fourcc; in isc_try_fmt()
878 pixfmt->colorspace = V4L2_COLORSPACE_SRGB; in isc_try_fmt()
879 pixfmt->field = V4L2_FIELD_NONE; in isc_try_fmt()
881 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3; in isc_try_fmt()
882 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) * in isc_try_fmt()
883 pixfmt->height; in isc_try_fmt()
885 isc->try_fmt = *f; in isc_try_fmt()
895 isc->config = isc->try_config; in isc_set_fmt()
896 isc->fmt = isc->try_fmt; in isc_set_fmt()
898 dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n", in isc_set_fmt()
899 (char *)&f->fmt.pix.pixelformat, in isc_set_fmt()
900 f->fmt.pix.width, f->fmt.pix.height); in isc_set_fmt()
908 media_entity_to_video_device(link->sink->entity); in isc_link_validate()
913 struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix; in isc_link_validate()
916 .pad = isc->remote_pad, in isc_link_validate()
920 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL, in isc_link_validate()
926 for (i = 0; i < isc->formats_list_size; i++) in isc_link_validate()
927 if (isc->formats_list[i].mbus_code == format.format.code) { in isc_link_validate()
928 sd_fmt = &isc->formats_list[i]; in isc_link_validate()
934 dev_err(isc->dev, in isc_link_validate()
937 return -EPIPE; in isc_link_validate()
941 isc->try_config.sd_format = sd_fmt; in isc_link_validate()
944 if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) in isc_link_validate()
948 v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0, in isc_link_validate()
949 &format.format.height, 16, isc->max_height, 0, 0); in isc_link_validate()
952 if (pixfmt->height != format.format.height || in isc_link_validate()
953 pixfmt->width != format.format.width) { in isc_link_validate()
954 dev_err(isc->dev, in isc_link_validate()
957 return -EPIPE; in isc_link_validate()
960 dev_dbg(isc->dev, in isc_link_validate()
962 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height, in isc_link_validate()
963 isc->try_config.bpp); in isc_link_validate()
966 if (isc->try_config.sd_format && isc->config.sd_format && in isc_link_validate()
967 isc->try_config.sd_format != isc->config.sd_format) { in isc_link_validate()
968 isc->ctrls.hist_stat = HIST_INIT; in isc_link_validate()
983 isc->config = isc->try_config; in isc_link_validate()
985 dev_dbg(isc->dev, "New ISC configuration in place\n"); in isc_link_validate()
995 if (vb2_is_busy(&isc->vb2_vidq)) in isc_s_fmt_vid_cap()
996 return -EBUSY; in isc_s_fmt_vid_cap()
1012 if (inp->index != 0) in isc_enum_input()
1013 return -EINVAL; in isc_enum_input()
1015 inp->type = V4L2_INPUT_TYPE_CAMERA; in isc_enum_input()
1016 inp->std = 0; in isc_enum_input()
1017 strscpy(inp->name, "Camera", sizeof(inp->name)); in isc_enum_input()
1032 return -EINVAL; in isc_s_input()
1041 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a); in isc_g_parm()
1048 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a); in isc_s_parm()
1055 int ret = -EINVAL; in isc_enum_framesizes()
1058 if (fsize->index) in isc_enum_framesizes()
1059 return -EINVAL; in isc_enum_framesizes()
1061 for (i = 0; i < isc->controller_formats_size; i++) in isc_enum_framesizes()
1062 if (isc->controller_formats[i].fourcc == fsize->pixel_format) in isc_enum_framesizes()
1068 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; in isc_enum_framesizes()
1070 fsize->stepwise.min_width = 16; in isc_enum_framesizes()
1071 fsize->stepwise.max_width = isc->max_width; in isc_enum_framesizes()
1072 fsize->stepwise.min_height = 16; in isc_enum_framesizes()
1073 fsize->stepwise.max_height = isc->max_height; in isc_enum_framesizes()
1074 fsize->stepwise.step_width = 1; in isc_enum_framesizes()
1075 fsize->stepwise.step_height = 1; in isc_enum_framesizes()
1113 struct v4l2_subdev *sd = isc->current_subdev->sd; in isc_open()
1116 if (mutex_lock_interruptible(&isc->lock)) in isc_open()
1117 return -ERESTARTSYS; in isc_open()
1127 if (ret < 0 && ret != -ENOIOCTLCMD) { in isc_open()
1132 ret = isc_set_fmt(isc, &isc->fmt); in isc_open()
1139 mutex_unlock(&isc->lock); in isc_open()
1146 struct v4l2_subdev *sd = isc->current_subdev->sd; in isc_release()
1150 mutex_lock(&isc->lock); in isc_release()
1159 mutex_unlock(&isc->lock); in isc_release()
1177 struct regmap *regmap = isc->regmap; in microchip_isc_interrupt()
1187 spin_lock(&isc->dma_queue_lock); in microchip_isc_interrupt()
1188 if (isc->cur_frm) { in microchip_isc_interrupt()
1189 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb; in microchip_isc_interrupt()
1190 struct vb2_buffer *vb = &vbuf->vb2_buf; in microchip_isc_interrupt()
1192 vb->timestamp = ktime_get_ns(); in microchip_isc_interrupt()
1193 vbuf->sequence = isc->sequence++; in microchip_isc_interrupt()
1195 isc->cur_frm = NULL; in microchip_isc_interrupt()
1198 if (!list_empty(&isc->dma_queue) && !isc->stop) { in microchip_isc_interrupt()
1199 isc->cur_frm = list_first_entry(&isc->dma_queue, in microchip_isc_interrupt()
1201 list_del(&isc->cur_frm->list); in microchip_isc_interrupt()
1206 if (isc->stop) in microchip_isc_interrupt()
1207 complete(&isc->comp); in microchip_isc_interrupt()
1210 spin_unlock(&isc->dma_queue_lock); in microchip_isc_interrupt()
1214 schedule_work(&isc->awb_work); in microchip_isc_interrupt()
1224 struct regmap *regmap = isc->regmap; in isc_hist_count()
1225 struct isc_ctrls *ctrls = &isc->ctrls; in isc_hist_count()
1226 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id]; in isc_hist_count()
1227 u32 *hist_entry = &ctrls->hist_entry[0]; in isc_hist_count()
1233 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, in isc_hist_count()
1252 dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u", in isc_hist_count()
1253 ctrls->hist_id, *hist_count); in isc_hist_count()
1259 u32 *hist_count = &ctrls->hist_count[0]; in isc_wb_update()
1260 u32 c, offset[4]; in isc_wb_update() local
1262 /* We compute two gains, stretch gain and grey world gain */ in isc_wb_update()
1275 dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg); in isc_wb_update()
1283 * the color offset is the minimum value of the histogram. in isc_wb_update()
1287 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX]; in isc_wb_update()
1289 * The offset is always at least 1. If the offset is 1, we do in isc_wb_update()
1291 * the offset is computed in a histogram on 9 bits (0..512) in isc_wb_update()
1292 * but the offset in register is based on in isc_wb_update()
1297 ctrls->offset[c] = (offset[c] - 1) << 3; in isc_wb_update()
1300 * the offset is then taken and converted to 2's complements, in isc_wb_update()
1304 ctrls->offset[c] = -ctrls->offset[c]; in isc_wb_update()
1307 * the stretch gain is the total number of histogram bins in isc_wb_update()
1308 * divided by the actual range of color component (Max - Min) in isc_wb_update()
1309 * If we compute gain like this, the actual color component in isc_wb_update()
1315 (ctrls->hist_minmax[c][HIST_MAX_INDEX] - in isc_wb_update()
1316 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); in isc_wb_update()
1319 * Now we have to compute the gain w.r.t. the average. in isc_wb_update()
1320 * Add/lose gain to the component towards the average. in isc_wb_update()
1322 * fixed point value : 1.0 gain. in isc_wb_update()
1329 dev_dbg(isc->dev, in isc_wb_update()
1333 ctrls->gain[c] = s_gain[c] * gw_gain[c]; in isc_wb_update()
1334 ctrls->gain[c] >>= 9; in isc_wb_update()
1337 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); in isc_wb_update()
1339 dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n", in isc_wb_update()
1340 c, ctrls->gain[c]); in isc_wb_update()
1348 struct regmap *regmap = isc->regmap; in isc_awb_work()
1349 struct isc_ctrls *ctrls = &isc->ctrls; in isc_awb_work()
1350 u32 hist_id = ctrls->hist_id; in isc_awb_work()
1356 if (ctrls->hist_stat != HIST_ENABLED) in isc_awb_work()
1361 dev_dbg(isc->dev, in isc_awb_work()
1364 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; in isc_awb_work()
1365 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; in isc_awb_work()
1374 ctrls->hist_id = hist_id; in isc_awb_work()
1375 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; in isc_awb_work()
1377 ret = pm_runtime_resume_and_get(isc->dev); in isc_awb_work()
1385 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) { in isc_awb_work()
1392 spin_lock_irqsave(&isc->awb_lock, flags); in isc_awb_work()
1394 spin_unlock_irqrestore(&isc->awb_lock, flags); in isc_awb_work()
1400 if (ctrls->awb == ISC_WB_ONETIME) { in isc_awb_work()
1401 dev_info(isc->dev, in isc_awb_work()
1402 "Completed one time white-balance adjustment.\n"); in isc_awb_work()
1405 ctrls->awb = ISC_WB_NONE; in isc_awb_work()
1408 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, in isc_awb_work()
1416 mutex_lock(&isc->awb_mutex); in isc_awb_work()
1419 if (isc->stop) { in isc_awb_work()
1420 mutex_unlock(&isc->awb_mutex); in isc_awb_work()
1426 mutex_unlock(&isc->awb_mutex); in isc_awb_work()
1429 if (ctrls->awb) in isc_awb_work()
1432 pm_runtime_put_sync(isc->dev); in isc_awb_work()
1437 struct isc_device *isc = container_of(ctrl->handler, in isc_s_ctrl()
1439 struct isc_ctrls *ctrls = &isc->ctrls; in isc_s_ctrl()
1441 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) in isc_s_ctrl()
1444 switch (ctrl->id) { in isc_s_ctrl()
1446 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; in isc_s_ctrl()
1449 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; in isc_s_ctrl()
1452 ctrls->gamma_index = ctrl->val; in isc_s_ctrl()
1455 return -EINVAL; in isc_s_ctrl()
1467 struct isc_device *isc = container_of(ctrl->handler, in isc_s_awb_ctrl()
1469 struct isc_ctrls *ctrls = &isc->ctrls; in isc_s_awb_ctrl()
1471 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) in isc_s_awb_ctrl()
1474 switch (ctrl->id) { in isc_s_awb_ctrl()
1476 if (ctrl->val == 1) in isc_s_awb_ctrl()
1477 ctrls->awb = ISC_WB_AUTO; in isc_s_awb_ctrl()
1479 ctrls->awb = ISC_WB_NONE; in isc_s_awb_ctrl()
1482 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) in isc_s_awb_ctrl()
1483 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val; in isc_s_awb_ctrl()
1484 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new) in isc_s_awb_ctrl()
1485 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val; in isc_s_awb_ctrl()
1486 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new) in isc_s_awb_ctrl()
1487 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val; in isc_s_awb_ctrl()
1488 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new) in isc_s_awb_ctrl()
1489 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val; in isc_s_awb_ctrl()
1491 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new) in isc_s_awb_ctrl()
1492 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val; in isc_s_awb_ctrl()
1493 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new) in isc_s_awb_ctrl()
1494 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val; in isc_s_awb_ctrl()
1495 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new) in isc_s_awb_ctrl()
1496 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val; in isc_s_awb_ctrl()
1497 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) in isc_s_awb_ctrl()
1498 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val; in isc_s_awb_ctrl()
1502 mutex_lock(&isc->awb_mutex); in isc_s_awb_ctrl()
1503 if (vb2_is_streaming(&isc->vb2_vidq)) { in isc_s_awb_ctrl()
1515 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_s_awb_ctrl()
1517 mutex_unlock(&isc->awb_mutex); in isc_s_awb_ctrl()
1520 if (ctrls->awb == ISC_WB_AUTO && in isc_s_awb_ctrl()
1521 vb2_is_streaming(&isc->vb2_vidq) && in isc_s_awb_ctrl()
1522 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) in isc_s_awb_ctrl()
1529 if (ctrls->awb == ISC_WB_NONE && in isc_s_awb_ctrl()
1530 ctrl->cluster[ISC_CTRL_DO_WB]->is_new && in isc_s_awb_ctrl()
1531 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags & in isc_s_awb_ctrl()
1533 ctrls->awb = ISC_WB_ONETIME; in isc_s_awb_ctrl()
1535 dev_dbg(isc->dev, "One time white-balance started.\n"); in isc_s_awb_ctrl()
1544 struct isc_device *isc = container_of(ctrl->handler, in isc_g_volatile_awb_ctrl()
1546 struct isc_ctrls *ctrls = &isc->ctrls; in isc_g_volatile_awb_ctrl()
1548 switch (ctrl->id) { in isc_g_volatile_awb_ctrl()
1551 ctrl->cluster[ISC_CTRL_R_GAIN]->val = in isc_g_volatile_awb_ctrl()
1552 ctrls->gain[ISC_HIS_CFG_MODE_R]; in isc_g_volatile_awb_ctrl()
1553 ctrl->cluster[ISC_CTRL_B_GAIN]->val = in isc_g_volatile_awb_ctrl()
1554 ctrls->gain[ISC_HIS_CFG_MODE_B]; in isc_g_volatile_awb_ctrl()
1555 ctrl->cluster[ISC_CTRL_GR_GAIN]->val = in isc_g_volatile_awb_ctrl()
1556 ctrls->gain[ISC_HIS_CFG_MODE_GR]; in isc_g_volatile_awb_ctrl()
1557 ctrl->cluster[ISC_CTRL_GB_GAIN]->val = in isc_g_volatile_awb_ctrl()
1558 ctrls->gain[ISC_HIS_CFG_MODE_GB]; in isc_g_volatile_awb_ctrl()
1560 ctrl->cluster[ISC_CTRL_R_OFF]->val = in isc_g_volatile_awb_ctrl()
1561 ctrls->offset[ISC_HIS_CFG_MODE_R]; in isc_g_volatile_awb_ctrl()
1562 ctrl->cluster[ISC_CTRL_B_OFF]->val = in isc_g_volatile_awb_ctrl()
1563 ctrls->offset[ISC_HIS_CFG_MODE_B]; in isc_g_volatile_awb_ctrl()
1564 ctrl->cluster[ISC_CTRL_GR_OFF]->val = in isc_g_volatile_awb_ctrl()
1565 ctrls->offset[ISC_HIS_CFG_MODE_GR]; in isc_g_volatile_awb_ctrl()
1566 ctrl->cluster[ISC_CTRL_GB_OFF]->val = in isc_g_volatile_awb_ctrl()
1567 ctrls->offset[ISC_HIS_CFG_MODE_GB]; in isc_g_volatile_awb_ctrl()
1585 .min = -4095, \
1591 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1592 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1593 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1594 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1609 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1610 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1611 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1612 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1617 struct isc_ctrls *ctrls = &isc->ctrls; in isc_ctrl_init()
1618 struct v4l2_ctrl_handler *hdl = &ctrls->handler; in isc_ctrl_init()
1621 ctrls->hist_stat = HIST_INIT; in isc_ctrl_init()
1629 isc->config_ctrls(isc, ops); in isc_ctrl_init()
1631 ctrls->brightness = 0; in isc_ctrl_init()
1633 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); in isc_ctrl_init()
1634 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, in isc_ctrl_init()
1635 isc->gamma_max); in isc_ctrl_init()
1636 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, in isc_ctrl_init()
1641 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, in isc_ctrl_init()
1645 if (!isc->do_wb_ctrl) { in isc_ctrl_init()
1646 ret = hdl->error; in isc_ctrl_init()
1651 v4l2_ctrl_activate(isc->do_wb_ctrl, false); in isc_ctrl_init()
1653 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); in isc_ctrl_init()
1654 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); in isc_ctrl_init()
1655 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL); in isc_ctrl_init()
1656 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL); in isc_ctrl_init()
1657 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL); in isc_ctrl_init()
1658 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL); in isc_ctrl_init()
1659 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL); in isc_ctrl_init()
1660 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL); in isc_ctrl_init()
1666 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true); in isc_ctrl_init()
1677 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_bound()
1683 if (video_is_registered(&isc->video_dev)) { in isc_async_bound()
1684 dev_err(isc->dev, "only supports one sub-device.\n"); in isc_async_bound()
1685 return -EBUSY; in isc_async_bound()
1688 subdev_entity->sd = subdev; in isc_async_bound()
1690 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, in isc_async_bound()
1693 dev_err(isc->dev, "failed to find pad for %s\n", subdev->name); in isc_async_bound()
1697 isc->remote_pad = pad; in isc_async_bound()
1706 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_unbind()
1708 mutex_destroy(&isc->awb_mutex); in isc_async_unbind()
1709 cancel_work_sync(&isc->awb_work); in isc_async_unbind()
1710 video_unregister_device(&isc->video_dev); in isc_async_unbind()
1711 v4l2_ctrl_handler_free(&isc->ctrls.handler); in isc_async_unbind()
1717 struct isc_format *fmt = &isc->formats_list[0]; in isc_find_format_by_code()
1720 for (i = 0; i < isc->formats_list_size; i++) { in isc_find_format_by_code()
1721 if (fmt->mbus_code == code) { in isc_find_format_by_code()
1741 .pixelformat = isc->controller_formats[0].fourcc, in isc_set_default_fmt()
1750 isc->fmt = f; in isc_set_default_fmt()
1756 struct isc_device *isc = container_of(notifier->v4l2_dev, in isc_async_complete()
1758 struct video_device *vdev = &isc->video_dev; in isc_async_complete()
1759 struct vb2_queue *q = &isc->vb2_vidq; in isc_async_complete()
1762 INIT_WORK(&isc->awb_work, isc_awb_work); in isc_async_complete()
1764 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); in isc_async_complete()
1766 dev_err(isc->dev, "Failed to register subdev nodes\n"); in isc_async_complete()
1770 isc->current_subdev = container_of(notifier, in isc_async_complete()
1772 mutex_init(&isc->lock); in isc_async_complete()
1773 mutex_init(&isc->awb_mutex); in isc_async_complete()
1775 init_completion(&isc->comp); in isc_async_complete()
1778 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; in isc_async_complete()
1779 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; in isc_async_complete()
1780 q->drv_priv = isc; in isc_async_complete()
1781 q->buf_struct_size = sizeof(struct isc_buffer); in isc_async_complete()
1782 q->ops = &isc_vb2_ops; in isc_async_complete()
1783 q->mem_ops = &vb2_dma_contig_memops; in isc_async_complete()
1784 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; in isc_async_complete()
1785 q->lock = &isc->lock; in isc_async_complete()
1786 q->min_queued_buffers = 1; in isc_async_complete()
1787 q->dev = isc->dev; in isc_async_complete()
1791 dev_err(isc->dev, "vb2_queue_init() failed: %d\n", ret); in isc_async_complete()
1796 INIT_LIST_HEAD(&isc->dma_queue); in isc_async_complete()
1797 spin_lock_init(&isc->dma_queue_lock); in isc_async_complete()
1798 spin_lock_init(&isc->awb_lock); in isc_async_complete()
1802 dev_err(isc->dev, "Could not set default format\n"); in isc_async_complete()
1808 dev_err(isc->dev, "Init isc ctrols failed: %d\n", ret); in isc_async_complete()
1813 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); in isc_async_complete()
1814 vdev->release = video_device_release_empty; in isc_async_complete()
1815 vdev->fops = &isc_fops; in isc_async_complete()
1816 vdev->ioctl_ops = &isc_ioctl_ops; in isc_async_complete()
1817 vdev->v4l2_dev = &isc->v4l2_dev; in isc_async_complete()
1818 vdev->vfl_dir = VFL_DIR_RX; in isc_async_complete()
1819 vdev->queue = q; in isc_async_complete()
1820 vdev->lock = &isc->lock; in isc_async_complete()
1821 vdev->ctrl_handler = &isc->ctrls.handler; in isc_async_complete()
1822 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE | in isc_async_complete()
1826 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); in isc_async_complete()
1828 dev_err(isc->dev, "video_register_device failed: %d\n", ret); in isc_async_complete()
1836 ret = media_device_register(&isc->mdev); in isc_async_complete()
1846 mutex_destroy(&isc->awb_mutex); in isc_async_complete()
1847 mutex_destroy(&isc->lock); in isc_async_complete()
1862 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { in microchip_isc_subdev_cleanup()
1863 v4l2_async_nf_unregister(&subdev_entity->notifier); in microchip_isc_subdev_cleanup()
1864 v4l2_async_nf_cleanup(&subdev_entity->notifier); in microchip_isc_subdev_cleanup()
1867 INIT_LIST_HEAD(&isc->subdev_entities); in microchip_isc_subdev_cleanup()
1873 struct device *dev = isc->dev; in microchip_isc_pipeline_init()
1874 struct regmap *regmap = isc->regmap; in microchip_isc_pipeline_init()
1879 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> in microchip_isc_pipeline_init()
1880 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 in microchip_isc_pipeline_init()
1894 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), in microchip_isc_pipeline_init()
1895 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), in microchip_isc_pipeline_init()
1896 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), in microchip_isc_pipeline_init()
1897 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), in microchip_isc_pipeline_init()
1905 isc->pipeline[i] = regs; in microchip_isc_pipeline_init()
1921 isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L; in isc_mc_init()
1922 isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT; in isc_mc_init()
1923 isc->video_dev.entity.ops = &isc_entity_operations; in isc_mc_init()
1925 isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK; in isc_mc_init()
1927 ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM, in isc_mc_init()
1928 isc->pads); in isc_mc_init()
1930 dev_err(isc->dev, "media entity init failed\n"); in isc_mc_init()
1934 isc->mdev.dev = isc->dev; in isc_mc_init()
1936 match = of_match_node(isc->dev->driver->of_match_table, in isc_mc_init()
1937 isc->dev->of_node); in isc_mc_init()
1939 strscpy(isc->mdev.driver_name, KBUILD_MODNAME, in isc_mc_init()
1940 sizeof(isc->mdev.driver_name)); in isc_mc_init()
1941 strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model)); in isc_mc_init()
1942 isc->mdev.hw_revision = ver; in isc_mc_init()
1944 media_device_init(&isc->mdev); in isc_mc_init()
1946 isc->v4l2_dev.mdev = &isc->mdev; in isc_mc_init()
1954 media_entity_cleanup(&isc->video_dev.entity); in isc_mc_cleanup()
1955 media_device_cleanup(&isc->mdev); in isc_mc_cleanup()