Lines Matching refs:MM_REG_WRITE
75 MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, in init_rdma()
80 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); in init_rdma()
82 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); in init_rdma()
101 MM_REG_WRITE(cmd, subsys_id, base, in config_rdma_frame()
104 MM_REG_WRITE(cmd, subsys_id, base, in config_rdma_frame()
109 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, in config_rdma_frame()
119 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, in config_rdma_frame()
129 MM_REG_WRITE(cmd, subsys_id, in config_rdma_frame()
137 MM_REG_WRITE(cmd, subsys_id, in config_rdma_frame()
147 MM_REG_WRITE(cmd, subsys_id, in config_rdma_frame()
160 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, in config_rdma_frame()
168 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, in config_rdma_frame()
175 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, in config_rdma_frame()
182 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, in config_rdma_frame()
190 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, in config_rdma_frame()
197 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, in config_rdma_frame()
204 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, in config_rdma_frame()
212 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, in config_rdma_frame()
219 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, in config_rdma_frame()
227 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, in config_rdma_frame()
235 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, in config_rdma_frame()
240 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, in config_rdma_frame()
245 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, in config_rdma_frame()
250 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, in config_rdma_frame()
255 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, in config_rdma_frame()
260 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, in config_rdma_frame()
265 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, in config_rdma_frame()
270 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, in config_rdma_frame()
275 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, in config_rdma_frame()
280 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, in config_rdma_frame()
300 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); in config_rdma_subfrm()
307 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, in config_rdma_subfrm()
317 MM_REG_WRITE(cmd, subsys_id, base, in config_rdma_subfrm()
328 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, in config_rdma_subfrm()
336 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, in config_rdma_subfrm()
344 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, in config_rdma_subfrm()
352 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, in config_rdma_subfrm()
360 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, in config_rdma_subfrm()
372 MM_REG_WRITE(cmd, subsys_id, base, in config_rdma_subfrm()
396 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); in wait_rdma_event()
414 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); in init_rsz()
415 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); in init_rsz()
417 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); in init_rsz()
440 MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); in config_rsz_frame()
449 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); in config_rsz_frame()
457 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, in config_rsz_frame()
464 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, in config_rsz_frame()
471 MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, in config_rsz_frame()
478 MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, in config_rsz_frame()
498 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, in config_rsz_subfrm()
505 MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, in config_rsz_subfrm()
517 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, in config_rsz_subfrm()
524 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, in config_rsz_subfrm()
531 MM_REG_WRITE(cmd, subsys_id, in config_rsz_subfrm()
539 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, in config_rsz_subfrm()
546 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, in config_rsz_subfrm()
553 MM_REG_WRITE(cmd, subsys_id, in config_rsz_subfrm()
561 MM_REG_WRITE(cmd, subsys_id, in config_rsz_subfrm()
569 MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, in config_rsz_subfrm()
598 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
600 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
602 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
604 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
608 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
610 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
637 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, in advance_rsz_subfrm()
658 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); in init_wrot()
663 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); in init_wrot()
665 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); in init_wrot()
684 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, in config_wrot_frame()
691 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, in config_wrot_frame()
698 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, in config_wrot_frame()
704 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, in config_wrot_frame()
709 MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, in config_wrot_frame()
715 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, in config_wrot_frame()
724 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, in config_wrot_frame()
730 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, in config_wrot_frame()
739 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, in config_wrot_frame()
747 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, in config_wrot_frame()
754 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, in config_wrot_frame()
762 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); in config_wrot_frame()
765 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, in config_wrot_frame()
769 MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); in config_wrot_frame()
778 MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, in config_wrot_frame()
787 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, in config_wrot_frame()
792 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, in config_wrot_frame()
811 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, in config_wrot_subfrm()
819 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, in config_wrot_subfrm()
827 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, in config_wrot_subfrm()
835 MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, in config_wrot_subfrm()
843 MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, in config_wrot_subfrm()
850 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, in config_wrot_subfrm()
857 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, in config_wrot_subfrm()
861 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); in config_wrot_subfrm()
884 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, in wait_wrot_event()
888 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); in wait_wrot_event()
907 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); in init_wdma()
909 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); in init_wdma()
921 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, in config_wdma_frame()
927 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg, in config_wdma_frame()
932 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg, in config_wdma_frame()
936 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg, in config_wdma_frame()
940 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg, in config_wdma_frame()
945 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, in config_wdma_frame()
950 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH, in config_wdma_frame()
953 MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, in config_wdma_frame()
969 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, in config_wdma_subfrm()
974 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, in config_wdma_subfrm()
979 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, in config_wdma_subfrm()
984 MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, in config_wdma_subfrm()
989 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, in config_wdma_subfrm()
994 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, in config_wdma_subfrm()
998 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); in config_wdma_subfrm()
1010 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); in wait_wdma_event()
1041 MM_REG_WRITE(cmd, subsys_id, base, in reset_luma_hist()
1058 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); in init_tdshp()
1060 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); in init_tdshp()
1075 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); in config_tdshp_frame()
1089 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, in config_tdshp_subfrm()
1094 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, in config_tdshp_subfrm()
1099 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, in config_tdshp_subfrm()
1104 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); in config_tdshp_subfrm()
1108 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); in config_tdshp_subfrm()
1125 MM_REG_WRITE(cmd, subsys_id, base, in init_color()
1127 MM_REG_WRITE(cmd, subsys_id, base, in init_color()
1129 MM_REG_WRITE(cmd, subsys_id, base, in init_color()
1133 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); in init_color()
1134 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); in init_color()
1137 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); in init_color()
1139 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); in init_color()
1154 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, in config_color_frame()
1169 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, in config_color_subfrm()
1174 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, in config_color_subfrm()
1193 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); in init_ccorr()
1195 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); in init_ccorr()
1217 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE, in config_ccorr_subfrm()
1234 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); in init_aal()
1249 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); in config_aal_frame()
1253 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); in config_aal_frame()
1267 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, in config_aal_subfrm()
1272 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, in config_aal_subfrm()
1277 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, in config_aal_subfrm()
1296 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); in init_hdr()
1311 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); in config_hdr_frame()
1315 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); in config_hdr_frame()
1329 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, in config_hdr_subfrm()
1334 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1338 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1342 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1346 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); in config_hdr_subfrm()
1350 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); in config_hdr_subfrm()
1354 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); in config_hdr_subfrm()
1359 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); in config_hdr_subfrm()
1376 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); in init_fg()
1377 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); in init_fg()
1392 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); in config_fg_frame()
1396 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); in config_fg_frame()
1410 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); in config_fg_subfrm()
1414 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); in config_fg_subfrm()
1431 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, in init_ovl()
1435 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, in init_ovl()
1437 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, in init_ovl()
1453 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); in config_ovl_frame()
1457 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); in config_ovl_frame()
1471 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, in config_ovl_subfrm()
1477 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, in config_ovl_subfrm()
1495 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, in init_pad()
1498 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, in init_pad()
1500 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, in init_pad()
1515 MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, in config_pad_subfrm()