117 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
118 		reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl);  in config_rdma_frame()
127 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
128 				reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y);  in config_rdma_frame()
135 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
136 				reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c);  in config_rdma_frame()
145 				else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
146 					reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl);  in config_rdma_frame()
156 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rdma_frame()
157 		reg = CFG_COMP(MT8195, ctx->param, rdma.control);  in config_rdma_frame()
166 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
167 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]);  in config_rdma_frame()
173 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
174 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]);  in config_rdma_frame()
180 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
181 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]);  in config_rdma_frame()
188 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
189 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]);  in config_rdma_frame()
195 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
196 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]);  in config_rdma_frame()
202 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
203 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]);  in config_rdma_frame()
210 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
211 		reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd);  in config_rdma_frame()
217 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
218 		reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd);  in config_rdma_frame()
225 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
226 		reg = CFG_COMP(MT8195, ctx->param, rdma.transform);  in config_rdma_frame()
233 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
234 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0);  in config_rdma_frame()
238 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
239 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0);  in config_rdma_frame()
243 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
244 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0);  in config_rdma_frame()
248 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
249 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1);  in config_rdma_frame()
253 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
254 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1);  in config_rdma_frame()
258 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
259 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1);  in config_rdma_frame()
263 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
264 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2);  in config_rdma_frame()
268 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
269 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2);  in config_rdma_frame()
273 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
274 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2);  in config_rdma_frame()
278 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
279 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3);  in config_rdma_frame()
305 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
306 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]);  in config_rdma_subfrm()
315 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
316 				reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p);  in config_rdma_subfrm()
326 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
327 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]);  in config_rdma_subfrm()
334 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
335 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]);  in config_rdma_subfrm()
342 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
343 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src);  in config_rdma_subfrm()
350 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
351 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip);  in config_rdma_subfrm()
358 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
359 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst);  in config_rdma_subfrm()
366 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rdma_subfrm()
367 		csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in config_rdma_subfrm()
368 		csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in config_rdma_subfrm()
419 	if (CFG_CHECK(MT8195, p_id)) {  in init_rsz()
444 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
445 		bypass = CFG_COMP(MT8195, ctx->param, frame.bypass);  in config_rsz_frame()
455 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
456 		reg = CFG_COMP(MT8195, ctx->param, rsz.control1);  in config_rsz_frame()
462 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
463 		reg = CFG_COMP(MT8195, ctx->param, rsz.control2);  in config_rsz_frame()
469 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
470 		reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x);  in config_rsz_frame()
476 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
477 		reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y);  in config_rsz_frame()
496 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
497 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2);  in config_rsz_subfrm()
503 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
504 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src);  in config_rsz_subfrm()
511 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rsz_subfrm()
512 		csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in config_rsz_subfrm()
513 		csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in config_rsz_subfrm()
522 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
523 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left);  in config_rsz_subfrm()
529 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
530 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix);  in config_rsz_subfrm()
537 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
538 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top);  in config_rsz_subfrm()
544 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
545 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix);  in config_rsz_subfrm()
551 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
552 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left);  in config_rsz_subfrm()
559 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
560 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix);  in config_rsz_subfrm()
567 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
568 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip);  in config_rsz_subfrm()
572 	if (CFG_CHECK(MT8195, p_id)) {  in config_rsz_subfrm()
589 		if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
590 			reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch);  in config_rsz_subfrm()
596 		if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
597 			reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg);  in config_rsz_subfrm()
631 		} else if (CFG_CHECK(MT8195, p_id)) {  in advance_rsz_subfrm()
632 			csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in advance_rsz_subfrm()
633 			csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in advance_rsz_subfrm()
662 	if (CFG_CHECK(MT8195, p_id))  in init_wrot()
682 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
683 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]);  in config_wrot_frame()
689 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
690 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]);  in config_wrot_frame()
696 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
697 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]);  in config_wrot_frame()
702 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
703 			reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit);  in config_wrot_frame()
707 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
708 			reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero);  in config_wrot_frame()
713 	if (CFG_CHECK(MT8195, p_id)) {  in config_wrot_frame()
714 		reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number);  in config_wrot_frame()
722 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
723 		reg = CFG_COMP(MT8195, ctx->param, wrot.control);  in config_wrot_frame()
728 	if (CFG_CHECK(MT8195, p_id)) {  in config_wrot_frame()
729 		reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra);  in config_wrot_frame()
737 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
738 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]);  in config_wrot_frame()
745 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
746 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]);  in config_wrot_frame()
752 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
753 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]);  in config_wrot_frame()
760 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
761 		reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl);  in config_wrot_frame()
774 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
775 		reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test);  in config_wrot_frame()
785 		else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
786 			reg = CFG_COMP(MT8195, ctx->param, wrot.filter);  in config_wrot_frame()
791 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
809 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
810 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]);  in config_wrot_subfrm()
817 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
818 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]);  in config_wrot_subfrm()
825 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
826 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]);  in config_wrot_subfrm()
833 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
834 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src);  in config_wrot_subfrm()
841 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
842 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip);  in config_wrot_subfrm()
848 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
849 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst);  in config_wrot_subfrm()
855 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
856 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf);  in config_wrot_subfrm()
1073 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_frame()
1074 		reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg);  in config_tdshp_frame()
1087 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1088 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src);  in config_tdshp_subfrm()
1092 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1093 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst);  in config_tdshp_subfrm()
1097 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1098 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip);  in config_tdshp_subfrm()
1102 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1103 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0);  in config_tdshp_subfrm()
1106 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1107 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1);  in config_tdshp_subfrm()
1152 	if (CFG_CHECK(MT8195, p_id))  in config_color_frame()
1153 		reg = CFG_COMP(MT8195, ctx->param, color.start);  in config_color_frame()
1167 	if (CFG_CHECK(MT8195, p_id))  in config_color_subfrm()
1168 		reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize);  in config_color_subfrm()
1172 	if (CFG_CHECK(MT8195, p_id))  in config_color_subfrm()
1173 		reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize);  in config_color_subfrm()
1247 	if (CFG_CHECK(MT8195, p_id))  in config_aal_frame()
1248 		reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main);  in config_aal_frame()
1251 	if (CFG_CHECK(MT8195, p_id))  in config_aal_frame()
1252 		reg = CFG_COMP(MT8195, ctx->param, aal.cfg);  in config_aal_frame()
1265 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1266 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src);  in config_aal_subfrm()
1270 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1271 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst);  in config_aal_subfrm()
1275 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1276 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip);  in config_aal_subfrm()
1309 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_frame()
1310 		reg = CFG_COMP(MT8195, ctx->param, hdr.top);  in config_hdr_frame()
1313 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_frame()
1314 		reg = CFG_COMP(MT8195, ctx->param, hdr.relay);  in config_hdr_frame()
1327 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1328 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size);  in config_hdr_subfrm()
1332 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1333 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src);  in config_hdr_subfrm()
1336 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1337 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0);  in config_hdr_subfrm()
1340 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1341 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1);  in config_hdr_subfrm()
1344 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1345 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0);  in config_hdr_subfrm()
1348 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1349 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1);  in config_hdr_subfrm()
1352 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1353 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top);  in config_hdr_subfrm()
1357 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1358 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr);  in config_hdr_subfrm()
1390 	if (CFG_CHECK(MT8195, p_id))  in config_fg_frame()
1391 		reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0);  in config_fg_frame()
1394 	if (CFG_CHECK(MT8195, p_id))  in config_fg_frame()
1395 		reg = CFG_COMP(MT8195, ctx->param, fg.ck_en);  in config_fg_frame()
1408 	if (CFG_CHECK(MT8195, p_id))  in config_fg_subfrm()
1409 		reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0);  in config_fg_subfrm()
1412 	if (CFG_CHECK(MT8195, p_id))  in config_fg_subfrm()
1413 		reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1);  in config_fg_subfrm()
1451 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_frame()
1452 		reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con);  in config_ovl_frame()
1455 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_frame()
1456 		reg = CFG_COMP(MT8195, ctx->param, ovl.src_con);  in config_ovl_frame()
1469 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_subfrm()
1470 		reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size);  in config_ovl_subfrm()
1475 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_subfrm()
1476 		reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size);  in config_ovl_subfrm()
1513 	if (CFG_CHECK(MT8195, p_id))  in config_pad_subfrm()
1514 		reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size);  in config_pad_subfrm()
1559 		.compatible = "mediatek,mt8195-mdp3-rdma",
1562 		.compatible = "mediatek,mt8195-mdp3-split",
1565 		.compatible = "mediatek,mt8195-mdp3-stitch",
1568 		.compatible = "mediatek,mt8195-mdp3-fg",
1571 		.compatible = "mediatek,mt8195-mdp3-hdr",
1574 		.compatible = "mediatek,mt8195-mdp3-aal",
1577 		.compatible = "mediatek,mt8195-mdp3-merge",
1580 		.compatible = "mediatek,mt8195-mdp3-tdshp",
1583 		.compatible = "mediatek,mt8195-mdp3-color",
1586 		.compatible = "mediatek,mt8195-mdp3-ovl",
1589 		.compatible = "mediatek,mt8195-mdp3-padding",
1592 		.compatible = "mediatek,mt8195-mdp3-tcc",
2038 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2039 		arg = CFG_COMP(MT8195, param, type);  in mdp_comp_ctx_config()
2057 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2058 		arg = CFG_COMP(MT8195, param, input);  in mdp_comp_ctx_config()
2064 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2065 		idx = CFG_COMP(MT8195, param, num_outputs);  in mdp_comp_ctx_config()
2071 		else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2072 			arg = CFG_COMP(MT8195, param, outputs[i]);  in mdp_comp_ctx_config()