Lines Matching +full:0 +full:x007fffff
76 0x0, BIT(0)); in init_rdma()
80 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); in init_rdma()
82 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); in init_rdma()
83 return 0; in init_rdma()
96 u32 rdma_con_mask = 0; in config_rdma_frame()
97 u32 reg = 0; in config_rdma_frame()
102 MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); in config_rdma_frame()
105 MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); in config_rdma_frame()
112 0x00030071); in config_rdma_frame()
120 0x03C8FE0F); in config_rdma_frame()
131 reg, 0xFFFFFFFF); in config_rdma_frame()
139 reg, 0xFFFFFFFF); in config_rdma_frame()
149 reg, 0x001FFFFF); in config_rdma_frame()
155 rdma_con_mask = 0x1110; in config_rdma_frame()
158 rdma_con_mask = 0x1130; in config_rdma_frame()
165 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); in config_rdma_frame()
167 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); in config_rdma_frame()
169 0xFFFFFFFF); in config_rdma_frame()
176 0xFFFFFFFF); in config_rdma_frame()
183 0xFFFFFFFF); in config_rdma_frame()
187 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
189 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
191 reg, 0xFFFFFFFF); in config_rdma_frame()
198 reg, 0xFFFFFFFF); in config_rdma_frame()
205 reg, 0xFFFFFFFF); in config_rdma_frame()
213 reg, 0x001FFFFF); in config_rdma_frame()
220 reg, 0x001FFFFF); in config_rdma_frame()
228 reg, 0x0F110000); in config_rdma_frame()
236 reg, 0x0FFF00FF); in config_rdma_frame()
241 reg, 0x3FFFFFFF); in config_rdma_frame()
246 reg, 0x3FFFFFFF); in config_rdma_frame()
251 reg, 0x0F7F007F); in config_rdma_frame()
256 reg, 0x3FFFFFFF); in config_rdma_frame()
261 reg, 0x3FFFFFFF); in config_rdma_frame()
266 reg, 0x0F3F003F); in config_rdma_frame()
271 reg, 0x3FFFFFFF); in config_rdma_frame()
276 reg, 0x3FFFFFFF); in config_rdma_frame()
281 reg, 0x0F3F003F); in config_rdma_frame()
284 return 0; in config_rdma_frame()
296 u32 csf_l = 0, csf_r = 0; in config_rdma_subfrm()
297 u32 reg = 0; in config_rdma_subfrm()
300 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); in config_rdma_subfrm()
304 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
306 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
308 reg, 0xFFFFFFFF); in config_rdma_subfrm()
319 reg, 0xFFFFFFFF); in config_rdma_subfrm()
329 reg, 0xFFFFFFFF); in config_rdma_subfrm()
337 reg, 0xFFFFFFFF); in config_rdma_subfrm()
345 0x1FFF1FFF); in config_rdma_subfrm()
353 reg, 0x1FFF1FFF); in config_rdma_subfrm()
361 reg, 0x003F001F); in config_rdma_subfrm()
375 return 0; in config_rdma_subfrm()
396 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); in wait_rdma_event()
397 return 0; in wait_rdma_event()
414 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); in init_rsz()
415 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); in init_rsz()
417 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); in init_rsz()
426 return 0; in init_rsz()
437 u32 reg = 0; in config_rsz_frame()
440 MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); in config_rsz_frame()
449 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); in config_rsz_frame()
450 return 0; in config_rsz_frame()
458 0x03FFFDF3); in config_rsz_frame()
465 0x0FFFC290); in config_rsz_frame()
472 reg, 0x007FFFFF); in config_rsz_frame()
479 reg, 0x007FFFFF); in config_rsz_frame()
481 return 0; in config_rsz_frame()
490 u32 csf_l = 0, csf_r = 0; in config_rsz_subfrm()
491 u32 reg = 0; in config_rsz_subfrm()
499 0x00003800); in config_rsz_subfrm()
506 0xFFFFFFFF); in config_rsz_subfrm()
525 reg, 0xFFFF); in config_rsz_subfrm()
533 reg, 0x1FFFFF); in config_rsz_subfrm()
540 reg, 0xFFFF); in config_rsz_subfrm()
547 reg, 0x1FFFFF); in config_rsz_subfrm()
555 reg, 0xFFFF); in config_rsz_subfrm()
563 reg, 0x1FFFFF); in config_rsz_subfrm()
570 0xFFFFFFFF); in config_rsz_subfrm()
599 MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); in config_rsz_subfrm()
601 MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); in config_rsz_subfrm()
603 MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); in config_rsz_subfrm()
605 MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); in config_rsz_subfrm()
609 MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); in config_rsz_subfrm()
611 MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); in config_rsz_subfrm()
615 return 0; in config_rsz_subfrm()
626 u32 csf_l = 0, csf_r = 0; in advance_rsz_subfrm()
637 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, in advance_rsz_subfrm()
641 return 0; in advance_rsz_subfrm()
658 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); in init_wrot()
659 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); in init_wrot()
663 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); in init_wrot()
665 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); in init_wrot()
666 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); in init_wrot()
667 return 0; in init_wrot()
677 u32 reg = 0; in config_wrot_frame()
681 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); in config_wrot_frame()
683 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); in config_wrot_frame()
685 0xFFFFFFFF); in config_wrot_frame()
692 0xFFFFFFFF); in config_wrot_frame()
699 0xFFFFFFFF); in config_wrot_frame()
705 reg, 0x0000000F); in config_wrot_frame()
710 reg, 0x04000000); in config_wrot_frame()
716 reg, 0x00000007); in config_wrot_frame()
725 0xF131510F); in config_wrot_frame()
731 0x00FFFFFF); in config_wrot_frame()
736 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); in config_wrot_frame()
738 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); in config_wrot_frame()
740 0x0000FFFF); in config_wrot_frame()
748 0xFFFF); in config_wrot_frame()
755 0xFFFF); in config_wrot_frame()
762 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); in config_wrot_frame()
764 /* Set the fixed ALPHA as 0xFF */ in config_wrot_frame()
765 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, in config_wrot_frame()
766 0xFF000000); in config_wrot_frame()
777 if (reg != 0) in config_wrot_frame()
779 reg, 0xFFF); in config_wrot_frame()
788 reg, 0x77); in config_wrot_frame()
793 (0x1 << 23) + (0x1 << 20), 0x900000); in config_wrot_frame()
796 return 0; in config_wrot_frame()
804 u32 reg = 0; in config_wrot_subfrm()
808 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
810 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
812 reg, 0x0FFFFFFF); in config_wrot_subfrm()
820 reg, 0x0FFFFFFF); in config_wrot_subfrm()
828 reg, 0x0FFFFFFF); in config_wrot_subfrm()
836 0x1FFF1FFF); in config_wrot_subfrm()
844 0x1FFF1FFF); in config_wrot_subfrm()
851 0x1FFF1FFF); in config_wrot_subfrm()
858 reg, 0x1FFF7F00); in config_wrot_subfrm()
861 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); in config_wrot_subfrm()
863 return 0; in config_wrot_subfrm()
884 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, in wait_wrot_event()
885 0x77); in wait_wrot_event()
888 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); in wait_wrot_event()
890 return 0; in wait_wrot_event()
907 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); in init_wdma()
908 MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); in init_wdma()
909 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); in init_wdma()
910 return 0; in init_wdma()
919 u32 reg = 0; in config_wdma_frame()
921 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, in config_wdma_frame()
922 0xFFFFFFFF); in config_wdma_frame()
928 0x0F01B8F0); in config_wdma_frame()
931 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); in config_wdma_frame()
933 0xFFFFFFFF); in config_wdma_frame()
937 0xFFFFFFFF); in config_wdma_frame()
941 0xFFFFFFFF); in config_wdma_frame()
946 reg, 0x0000FFFF); in config_wdma_frame()
951 reg, 0x0000FFFF); in config_wdma_frame()
952 /* Set the fixed ALPHA as 0xFF */ in config_wdma_frame()
953 MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, in config_wdma_frame()
954 0x800000FF); in config_wdma_frame()
956 return 0; in config_wdma_frame()
964 u32 reg = 0; in config_wdma_subfrm()
968 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); in config_wdma_subfrm()
970 reg, 0x0FFFFFFF); in config_wdma_subfrm()
975 reg, 0x0FFFFFFF); in config_wdma_subfrm()
980 reg, 0x0FFFFFFF); in config_wdma_subfrm()
985 0x3FFF3FFF); in config_wdma_subfrm()
990 0x3FFF3FFF); in config_wdma_subfrm()
995 0x3FFF3FFF); in config_wdma_subfrm()
998 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); in config_wdma_subfrm()
1000 return 0; in config_wdma_subfrm()
1010 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); in wait_wdma_event()
1011 return 0; in wait_wdma_event()
1035 for (i = 0; i <= hist_num; i++) in reset_luma_hist()
1038 0, 0xFFFFFFFF); in reset_luma_hist()
1042 MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); in reset_luma_hist()
1045 for (i = 0; i < hist_num; i++) in reset_luma_hist()
1048 0, 0xFFFFFFFF); in reset_luma_hist()
1050 return 0; in reset_luma_hist()
1058 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); in init_tdshp()
1071 u32 reg = 0; in config_tdshp_frame()
1075 MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); in config_tdshp_frame()
1077 return 0; in config_tdshp_frame()
1085 u32 reg = 0; in config_tdshp_subfrm()
1095 reg, 0x00FF00FF); in config_tdshp_subfrm()
1104 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); in config_tdshp_subfrm()
1108 MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); in config_tdshp_subfrm()
1110 return 0; in config_tdshp_subfrm()
1126 MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); in init_color()
1128 MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); in init_color()
1130 MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); in init_color()
1133 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); in init_color()
1134 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); in init_color()
1137 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); in init_color()
1139 MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); in init_color()
1141 return 0; in init_color()
1150 u32 reg = 0; in config_color_frame()
1157 return 0; in config_color_frame()
1165 u32 reg = 0; in config_color_subfrm()
1170 reg, 0x00003FFF); in config_color_subfrm()
1175 reg, 0x00003FFF); in config_color_subfrm()
1177 return 0; in config_color_subfrm()
1193 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); in init_ccorr()
1195 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); in init_ccorr()
1196 return 0; in init_ccorr()
1204 u32 csf_l = 0, csf_r = 0; in config_ccorr_subfrm()
1205 u32 csf_t = 0, csf_b = 0; in config_ccorr_subfrm()
1218 (hsize << 16) + (vsize << 0), 0x1FFF1FFF); in config_ccorr_subfrm()
1219 return 0; in config_ccorr_subfrm()
1234 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); in init_aal()
1236 return 0; in init_aal()
1245 u32 reg = 0; in config_aal_frame()
1253 MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); in config_aal_frame()
1255 return 0; in config_aal_frame()
1263 u32 reg = 0; in config_aal_subfrm()
1273 reg, 0x00FF00FF); in config_aal_subfrm()
1280 return 0; in config_aal_subfrm()
1296 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); in init_hdr()
1298 return 0; in init_hdr()
1307 u32 reg = 0; in config_hdr_frame()
1315 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); in config_hdr_frame()
1317 return 0; in config_hdr_frame()
1325 u32 reg = 0; in config_hdr_subfrm()
1334 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1338 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1342 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); in config_hdr_subfrm()
1346 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); in config_hdr_subfrm()
1350 MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); in config_hdr_subfrm()
1361 return 0; in config_hdr_subfrm()
1377 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); in init_fg()
1379 return 0; in init_fg()
1388 u32 reg = 0; in config_fg_frame()
1392 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); in config_fg_frame()
1396 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); in config_fg_frame()
1398 return 0; in config_fg_frame()
1406 u32 reg = 0; in config_fg_subfrm()
1410 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); in config_fg_subfrm()
1414 MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); in config_fg_subfrm()
1416 return 0; in config_fg_subfrm()
1432 BIT(0), MDP_OVL_EN_MASK); in init_ovl()
1438 BIT(0), MDP_OVL_DP_CON_MASK); in init_ovl()
1440 return 0; in init_ovl()
1449 u32 reg = 0; in config_ovl_frame()
1457 MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); in config_ovl_frame()
1459 return 0; in config_ovl_frame()
1467 u32 reg = 0; in config_ovl_subfrm()
1480 return 0; in config_ovl_subfrm()
1499 0, MDP_PAD_W_SIZE_MASK); in init_pad()
1501 0, MDP_PAD_H_SIZE_MASK); in init_pad()
1503 return 0; in init_pad()
1511 u32 reg = 0; in config_pad_subfrm()
1518 return 0; in config_pad_subfrm()
1618 for (i = 0; i < mdp->mdp_data->comp_data_len; i++) in mdp_comp_get_id()
1632 if (ret < 0) { in mdp_comp_clock_on()
1640 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_on()
1652 return 0; in mdp_comp_clock_on()
1655 while (--i >= 0) { in mdp_comp_clock_on()
1670 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_off()
1684 for (i = 0; i < num; i++) { in mdp_comp_clocks_on()
1707 return 0; in mdp_comp_clocks_on()
1714 for (i = 0; i < num; i++) { in mdp_comp_clocks_off()
1738 int ret = 0; in mdp_get_subsys_id()
1739 int index = 0; in mdp_get_subsys_id()
1754 if (ret != 0) { in mdp_get_subsys_id()
1764 return 0; in mdp_get_subsys_id()
1775 if (of_address_to_resource(node, index, &res) < 0) in __mdp_comp_init()
1776 base = 0L; in __mdp_comp_init()
1781 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
1794 if (id < 0 || id >= MDP_MAX_COMP_COUNT) { in mdp_comp_init()
1822 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_init()
1851 return 0; in mdp_comp_init()
1901 int ret = 0; in mdp_comp_sub_create()
1923 if (id < 0) { in mdp_comp_sub_create()
1949 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
1966 memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); in mdp_comp_config()
1990 if (id < 0) { in mdp_comp_config()
2015 return 0; in mdp_comp_config()
2043 if (public_id < 0) { in mdp_comp_ctx_config()
2068 for (i = 0; i < idx; i++) { in mdp_comp_ctx_config()
2077 return 0; in mdp_comp_ctx_config()