Lines Matching +full:0 +full:x0000000f
14 #define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)
18 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)
19 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)
21 #define MMU_MMU_TILE_CFG_OFFSET (0x0040)
25 #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)
28 #define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)
31 #define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)
32 #define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)
34 #define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)
38 #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFFF)
39 #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_SHIFT (0)
41 #define MMU_MMU_TILE_MAX_ADDR_OFFSET (0x0060)
45 #define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_MASK (0xFFFFFFFF)
46 #define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_SHIFT (0)
48 #define MMU_MMU_CONTROL0_OFFSET (0x0000)
50 #define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_MASK (0x00000001)
51 #define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_SHIFT (0)
53 #define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_MASK (0x00000100)
56 #define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_MASK (0x00000200)
59 #define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_MASK (0x00001000)
62 #define MMU_MMU_CONTROL1_OFFSET (0x0008)
64 #define MMU_MMU_CONTROL1_MMU_FLUSH_MASK (0x00000008)
69 #define MMU_MMU_CONTROL1_MMU_INVALDC_MASK (0x00000800)
74 #define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_MASK (0x00010000)
77 #define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_MASK (0x00100000)
80 #define MMU_MMU_CONTROL1_MMU_PAUSE_SET_MASK (0x01000000)
83 #define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_MASK (0x02000000)
86 #define MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK (0x10000000)
89 #define MMU_MMU_BANK_INDEX_OFFSET (0x0010)
91 #define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_MASK (0xC0000000)
96 #define MMU_REQUEST_PRIORITY_ENABLE_OFFSET (0x0018)
98 #define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_MASK (0x00008000)
103 #define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_MASK (0x00010000)
106 #define MMU_REQUEST_LIMITED_THROUGHPUT_OFFSET (0x001C)
108 #define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_MASK (0x000003FF)
109 #define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_SHIFT (0)
111 #define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_MASK (0x0FFF0000)
114 #define MMU_MMU_ADDRESS_CONTROL_OFFSET (0x0070)
117 #define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK (0x00000001)
118 #define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT (0)
120 #define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_MASK (0x00000010)
123 #define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_MASK (0x00FF0000)
126 #define MMU_MMU_CONFIG0_OFFSET (0x0080)
128 #define MMU_MMU_CONFIG0_NUM_REQUESTORS_MASK (0x0000000F)
129 #define MMU_MMU_CONFIG0_NUM_REQUESTORS_SHIFT (0)
131 #define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_MASK (0x000000F0)
134 #define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_MASK (0x00000700)
137 #define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_MASK (0x00001000)
140 #define MMU_MMU_CONFIG0_MMU_SUPPORTED_MASK (0x00002000)
143 #define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_MASK (0x001F0000)
146 #define MMU_MMU_CONFIG0_NO_READ_REORDER_MASK (0x00200000)
149 #define MMU_MMU_CONFIG0_TAGS_SUPPORTED_MASK (0xFFC00000)
152 #define MMU_MMU_CONFIG1_OFFSET (0x0084)
154 #define MMU_MMU_CONFIG1_PAGE_SIZE_MASK (0x0000000F)
155 #define MMU_MMU_CONFIG1_PAGE_SIZE_SHIFT (0)
157 #define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_MASK (0x0000FF00)
160 #define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_MASK (0x001F0000)
163 #define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_MASK (0x01000000)
166 #define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_MASK (0x02000000)
169 #define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_MASK (0x04000000)
172 #define MMU_MMU_STATUS0_OFFSET (0x0088)
174 #define MMU_MMU_STATUS0_MMU_PF_N_RW_MASK (0x00000001)
175 #define MMU_MMU_STATUS0_MMU_PF_N_RW_SHIFT (0)
177 #define MMU_MMU_STATUS0_MMU_FAULT_ADDR_MASK (0xFFFFF000)
180 #define MMU_MMU_STATUS1_OFFSET (0x008C)
182 #define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_MASK (0x0000FFFF)
183 #define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_SHIFT (0)
185 #define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_MASK (0x000F0000)
188 #define MMU_MMU_STATUS1_MMU_FAULT_INDEX_MASK (0x03000000)
191 #define MMU_MMU_STATUS1_MMU_FAULT_RNW_MASK (0x10000000)
194 #define MMU_MMU_MEM_REQ_OFFSET (0x0090)
196 #define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_MASK (0x000003FF)
197 #define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_SHIFT (0)
199 #define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_MASK (0x00001000)
202 #define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_MASK (0x00002000)
205 #define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_MASK (0x00004000)
208 #define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_MASK (0x80000000)
213 #define MMU_MMU_FAULT_SELECT_OFFSET (0x00A0)
215 #define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_MASK (0x0000000F)
216 #define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_SHIFT (0)
218 #define MMU_PROTOCOL_FAULT_OFFSET (0x00A8)
220 #define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_MASK (0x00000001)
221 #define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_SHIFT (0)
223 #define MMU_PROTOCOL_FAULT_FAULT_WRITE_MASK (0x00000010)
226 #define MMU_PROTOCOL_FAULT_FAULT_READ_MASK (0x00000020)
229 #define MMU_TOTAL_READ_REQ_OFFSET (0x0100)
231 #define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_MASK (0xFFFFFFFF)
232 #define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_SHIFT (0)
234 #define MMU_TOTAL_WRITE_REQ_OFFSET (0x0104)
236 #define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_MASK (0xFFFFFFFF)
237 #define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_SHIFT (0)
239 #define MMU_READS_LESS_64_REQ_OFFSET (0x0108)
241 #define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_MASK (0xFFFFFFFF)
242 #define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_SHIFT (0)
244 #define MMU_WRITES_LESS_64_REQ_OFFSET (0x010C)
246 #define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_MASK (0xFFFFFFFF)
247 #define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_SHIFT (0)
249 #define MMU_EXT_CMD_STALL_OFFSET (0x0120)
251 #define MMU_EXT_CMD_STALL_EXT_CMD_STALL_MASK (0xFFFFFFFF)
252 #define MMU_EXT_CMD_STALL_EXT_CMD_STALL_SHIFT (0)
254 #define MMU_WRITE_REQ_STALL_OFFSET (0x0124)
256 #define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_MASK (0xFFFFFFFF)
257 #define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_SHIFT (0)
259 #define MMU_MMU_MISS_STALL_OFFSET (0x0128)
261 #define MMU_MMU_MISS_STALL_MMU_MISS_STALL_MASK (0xFFFFFFFF)
262 #define MMU_MMU_MISS_STALL_MMU_MISS_STALL_SHIFT (0)
264 #define MMU_ADDRESS_STALL_OFFSET (0x012C)
266 #define MMU_ADDRESS_STALL_ADDRESS_STALL_MASK (0xFFFFFFFF)
267 #define MMU_ADDRESS_STALL_ADDRESS_STALL_SHIFT (0)
269 #define MMU_TAG_STALL_OFFSET (0x0130)
271 #define MMU_TAG_STALL_TAG_STALL_MASK (0xFFFFFFFF)
272 #define MMU_TAG_STALL_TAG_STALL_SHIFT (0)
274 #define MMU_PEAK_READ_OUTSTANDING_OFFSET (0x0140)
276 #define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_MASK (0x000003FF)
277 #define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_SHIFT (0)
279 #define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_MASK (0xFFFF0000)
282 #define MMU_AVERAGE_READ_LATENCY_OFFSET (0x0144)
284 #define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_MASK (0xFFFFFFFF)
285 #define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_SHIFT (0)
287 #define MMU_STATISTICS_CONTROL_OFFSET (0x0160)
289 #define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_MASK (0x00000001)
290 #define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_SHIFT (0)
292 #define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_MASK (0x00000002)
295 #define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_MASK (0x00000004)
298 #define MMU_MMU_VERSION_OFFSET (0x01D0)
300 #define MMU_MMU_VERSION_MMU_MAJOR_REV_MASK (0x00FF0000)
303 #define MMU_MMU_VERSION_MMU_MINOR_REV_MASK (0x0000FF00)
306 #define MMU_MMU_VERSION_MMU_MAINT_REV_MASK (0x000000FF)
307 #define MMU_MMU_VERSION_MMU_MAINT_REV_SHIFT (0)
309 #define MMU_BYTE_SIZE (0x01D4)