Lines Matching refs:vpu_read_reg
92 reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); in _wave5_print_reg_err()
185 return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0; in wave5_vpu_is_init()
190 u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); in wave5_vpu_get_product_id()
244 if (!vpu_read_reg(dev, W5_RET_SUCCESS)) { in wave5_vpu_firmware_command_queue_error_check()
245 reason = vpu_read_reg(dev, W5_RET_FAIL_REASON); in wave5_vpu_firmware_command_queue_error_check()
279 *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in send_firmware_command()
342 reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); in setup_wave5_properties()
351 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); in setup_wave5_properties()
352 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in setup_wave5_properties()
353 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); in setup_wave5_properties()
354 hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); in setup_wave5_properties()
355 hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); in setup_wave5_properties()
356 hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); in setup_wave5_properties()
400 reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in wave5_vpu_get_version()
474 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_init()
586 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_dec_param()
672 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_get_dec_seq_result()
674 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_get_dec_seq_result()
677 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); in wave5_get_dec_seq_result()
679 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); in wave5_get_dec_seq_result()
682 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); in wave5_get_dec_seq_result()
686 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); in wave5_get_dec_seq_result()
690 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); in wave5_get_dec_seq_result()
712 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_get_dec_seq_result()
713 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_get_dec_seq_result()
734 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_seq_info()
743 if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { in wave5_vpu_dec_get_seq_info()
744 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); in wave5_vpu_dec_get_seq_info()
897 reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); in wave5_vpu_dec_register_framebuffer()
1014 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_result()
1022 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); in wave5_vpu_dec_get_result()
1050 index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); in wave5_vpu_dec_get_result()
1052 index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); in wave5_vpu_dec_get_result()
1056 sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); in wave5_vpu_dec_get_result()
1063 result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); in wave5_vpu_dec_get_result()
1066 result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); in wave5_vpu_dec_get_result()
1067 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_vpu_dec_get_result()
1077 result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); in wave5_vpu_dec_get_result()
1078 result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); in wave5_vpu_dec_get_result()
1130 old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); in wave5_vpu_re_init()
1168 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_re_init()
1295 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_sleep_wake()
1363 val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_reset()
1485 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_dec_clr_disp_flag()
1508 interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); in wave5_vpu_clear_interrupt()
1523 return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1595 p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_enc_param()
1884 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_seq_info()
1889 if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { in wave5_vpu_enc_get_seq_info()
1890 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_seq_info()
1893 info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_seq_info()
1896 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); in wave5_vpu_enc_get_seq_info()
1897 info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); in wave5_vpu_enc_get_seq_info()
1898 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1899 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
2333 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_result()
2338 encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); in wave5_vpu_enc_get_result()
2340 result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_result()
2344 result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_result()
2346 reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); in wave5_vpu_enc_get_result()
2349 result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); in wave5_vpu_enc_get_result()
2354 result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); in wave5_vpu_enc_get_result()
2355 result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); in wave5_vpu_enc_get_result()
2356 result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); in wave5_vpu_enc_get_result()
2357 p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); in wave5_vpu_enc_get_result()
2358 p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2360 result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2372 result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); in wave5_vpu_enc_get_result()
2373 result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); in wave5_vpu_enc_get_result()