Lines Matching refs:vpu_dev
44 static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,
84 static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, in _wave5_print_reg_err() argument
87 struct device *dev = vpu_dev->dev; in _wave5_print_reg_err()
92 reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); in _wave5_print_reg_err()
122 static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) in wave5_wait_fio_readl() argument
128 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); in wave5_wait_fio_readl()
130 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); in wave5_wait_fio_readl()
134 if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val) in wave5_wait_fio_readl()
140 static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data) in wave5_fio_writel() argument
145 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data); in wave5_fio_writel()
148 wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); in wave5_fio_writel()
150 FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); in wave5_fio_writel()
152 dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", in wave5_fio_writel()
156 static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) in wave5_wait_bus_busy() argument
160 if (vpu_dev->product_code == WAVE515_CODE) in wave5_wait_bus_busy()
162 if (vpu_dev->product_code == WAVE521C_CODE || in wave5_wait_bus_busy()
163 vpu_dev->product_code == WAVE521_CODE || in wave5_wait_bus_busy()
164 vpu_dev->product_code == WAVE521E1_CODE) in wave5_wait_bus_busy()
167 return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value); in wave5_wait_bus_busy()
170 static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr) in wave5_wait_vpu_busy() argument
175 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr); in wave5_wait_vpu_busy()
178 static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) in wave5_wait_vcpu_bus_busy() argument
180 return wave5_wait_fio_readl(vpu_dev, addr, 0); in wave5_wait_vcpu_bus_busy()
183 bool wave5_vpu_is_init(struct vpu_device *vpu_dev) in wave5_vpu_is_init() argument
185 return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0; in wave5_vpu_is_init()
188 unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) in wave5_vpu_get_product_id() argument
190 u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); in wave5_vpu_get_product_id()
203 dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); in wave5_vpu_get_product_id()
206 dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); in wave5_vpu_get_product_id()
213 static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd) in wave5_bit_issue_command() argument
222 vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) | in wave5_bit_issue_command()
224 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_bit_issue_command()
227 vpu_write_reg(vpu_dev, W5_COMMAND, cmd); in wave5_bit_issue_command()
230 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, in wave5_bit_issue_command()
233 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); in wave5_bit_issue_command()
236 vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); in wave5_bit_issue_command()
290 static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst, in wave5_send_query() argument
295 vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt); in wave5_send_query()
296 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_send_query()
297 wave5_bit_issue_command(vpu_dev, inst, W5_QUERY); in wave5_send_query()
299 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_send_query()
301 dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); in wave5_send_query()
305 return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); in wave5_send_query()
308 static void setup_wave5_interrupts(struct vpu_device *vpu_dev) in setup_wave5_interrupts() argument
312 if (vpu_dev->attr.support_encoders) { in setup_wave5_interrupts()
319 if (vpu_dev->attr.support_decoders) { in setup_wave5_interrupts()
326 return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); in setup_wave5_interrupts()
331 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in setup_wave5_properties() local
332 struct vpu_attr *p_attr = &vpu_dev->attr; in setup_wave5_properties()
338 ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); in setup_wave5_properties()
342 reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); in setup_wave5_properties()
350 p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); in setup_wave5_properties()
351 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); in setup_wave5_properties()
352 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in setup_wave5_properties()
353 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); in setup_wave5_properties()
354 hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); in setup_wave5_properties()
355 hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); in setup_wave5_properties()
356 hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); in setup_wave5_properties()
358 if (vpu_dev->product_code == WAVE515_CODE) { in setup_wave5_properties()
386 setup_wave5_interrupts(vpu_dev); in setup_wave5_properties()
391 int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) in wave5_vpu_get_version() argument
396 ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); in wave5_vpu_get_version()
400 reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in wave5_vpu_get_version()
409 static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) in remap_page() argument
411 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index)); in remap_page()
412 vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); in remap_page()
413 vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); in remap_page()
423 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_init() local
425 common_vb = &vpu_dev->common_mem; in wave5_vpu_init()
429 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_init()
442 ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); in wave5_vpu_init()
444 dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", in wave5_vpu_init()
449 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); in wave5_vpu_init()
454 vpu_write_reg(vpu_dev, i, 0x00); in wave5_vpu_init()
456 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); in wave5_vpu_init()
457 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); in wave5_vpu_init()
459 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); in wave5_vpu_init()
460 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); in wave5_vpu_init()
461 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); in wave5_vpu_init()
462 vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); in wave5_vpu_init()
463 vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); in wave5_vpu_init()
466 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); in wave5_vpu_init()
468 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_init()
469 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); in wave5_vpu_init()
470 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); in wave5_vpu_init()
471 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); in wave5_vpu_init()
474 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_init()
484 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); in wave5_vpu_init()
487 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_init()
490 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, WAVE515_COMMAND_QUEUE_DEPTH); in wave5_vpu_init()
491 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, WAVE515_ONE_TASKBUF_SIZE); in wave5_vpu_init()
496 vpu_write_reg(vpu_dev, in wave5_vpu_init()
501 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_init()
502 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_init()
505 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_vpu_init()
506 vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); in wave5_vpu_init()
507 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); in wave5_vpu_init()
508 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_vpu_init()
510 dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_init()
514 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); in wave5_vpu_init()
526 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_build_up_dec_param() local
529 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_dec_param()
545 if (vpu_dev->product == PRODUCT_ID_515) in wave5_vpu_build_up_dec_param()
563 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_dec_param()
564 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_dec_param()
582 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
1003 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_dec_get_result() local
1010 ret = wave5_send_query(vpu_dev, inst, GET_RESULT); in wave5_vpu_dec_get_result()
1084 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1088 (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_dec_get_result()
1090 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1091 if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) in wave5_vpu_dec_get_result()
1111 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_re_init() local
1113 common_vb = &vpu_dev->common_mem; in wave5_vpu_re_init()
1117 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_re_init()
1130 old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); in wave5_vpu_re_init()
1135 ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); in wave5_vpu_re_init()
1137 dev_err(vpu_dev->dev, in wave5_vpu_re_init()
1142 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); in wave5_vpu_re_init()
1146 dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); in wave5_vpu_re_init()
1150 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); in wave5_vpu_re_init()
1151 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); in wave5_vpu_re_init()
1153 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); in wave5_vpu_re_init()
1154 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); in wave5_vpu_re_init()
1155 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); in wave5_vpu_re_init()
1156 vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); in wave5_vpu_re_init()
1157 vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); in wave5_vpu_re_init()
1160 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); in wave5_vpu_re_init()
1162 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_re_init()
1163 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); in wave5_vpu_re_init()
1164 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); in wave5_vpu_re_init()
1165 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); in wave5_vpu_re_init()
1168 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_re_init()
1178 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); in wave5_vpu_re_init()
1181 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_re_init()
1185 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, in wave5_vpu_re_init()
1187 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, in wave5_vpu_re_init()
1193 vpu_write_reg(vpu_dev, in wave5_vpu_re_init()
1198 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, in wave5_vpu_re_init()
1199 vpu_dev->sram_buf.daddr); in wave5_vpu_re_init()
1200 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, in wave5_vpu_re_init()
1201 vpu_dev->sram_buf.size); in wave5_vpu_re_init()
1204 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_vpu_re_init()
1205 vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); in wave5_vpu_re_init()
1206 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); in wave5_vpu_re_init()
1208 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_vpu_re_init()
1210 dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_re_init()
1214 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); in wave5_vpu_re_init()
1229 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_sleep_wake() local
1233 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_vpu_sleep_wake()
1242 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_vpu_sleep_wake()
1243 vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU); in wave5_vpu_sleep_wake()
1245 vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); in wave5_vpu_sleep_wake()
1247 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_vpu_sleep_wake()
1251 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); in wave5_vpu_sleep_wake()
1255 common_vb = &vpu_dev->common_mem; in wave5_vpu_sleep_wake()
1259 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_sleep_wake()
1275 vpu_write_reg(vpu_dev, W5_PO_CONF, 0); in wave5_vpu_sleep_wake()
1277 remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); in wave5_vpu_sleep_wake()
1278 remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); in wave5_vpu_sleep_wake()
1280 vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); in wave5_vpu_sleep_wake()
1281 vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); in wave5_vpu_sleep_wake()
1282 vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); in wave5_vpu_sleep_wake()
1285 vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); in wave5_vpu_sleep_wake()
1287 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_sleep_wake()
1288 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); in wave5_vpu_sleep_wake()
1289 wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); in wave5_vpu_sleep_wake()
1290 vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); in wave5_vpu_sleep_wake()
1293 setup_wave5_interrupts(vpu_dev); in wave5_vpu_sleep_wake()
1295 reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_sleep_wake()
1305 wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); in wave5_vpu_sleep_wake()
1308 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_sleep_wake()
1312 vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, in wave5_vpu_sleep_wake()
1314 vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, in wave5_vpu_sleep_wake()
1320 vpu_write_reg(vpu_dev, in wave5_vpu_sleep_wake()
1325 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, in wave5_vpu_sleep_wake()
1326 vpu_dev->sram_buf.daddr); in wave5_vpu_sleep_wake()
1327 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, in wave5_vpu_sleep_wake()
1328 vpu_dev->sram_buf.size); in wave5_vpu_sleep_wake()
1331 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); in wave5_vpu_sleep_wake()
1332 vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU); in wave5_vpu_sleep_wake()
1334 vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); in wave5_vpu_sleep_wake()
1336 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); in wave5_vpu_sleep_wake()
1338 dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_sleep_wake()
1342 return wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); in wave5_vpu_sleep_wake()
1352 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_reset() local
1353 struct vpu_attr *p_attr = &vpu_dev->attr; in wave5_vpu_reset()
1355 vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); in wave5_vpu_reset()
1363 val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); in wave5_vpu_reset()
1378 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF); in wave5_vpu_reset()
1381 ret = wave5_wait_vcpu_bus_busy(vpu_dev, in wave5_vpu_reset()
1384 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); in wave5_vpu_reset()
1389 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); in wave5_vpu_reset()
1392 if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) { in wave5_vpu_reset()
1393 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); in wave5_vpu_reset()
1398 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7); in wave5_vpu_reset()
1401 if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) { in wave5_vpu_reset()
1402 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); in wave5_vpu_reset()
1409 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100); in wave5_vpu_reset()
1412 ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS); in wave5_vpu_reset()
1414 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); in wave5_vpu_reset()
1430 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val); in wave5_vpu_reset()
1432 ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_RESET_STATUS); in wave5_vpu_reset()
1434 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); in wave5_vpu_reset()
1437 vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); in wave5_vpu_reset()
1443 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); in wave5_vpu_reset()
1444 wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); in wave5_vpu_reset()
1446 wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); in wave5_vpu_reset()
1449 wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); in wave5_vpu_reset()
1547 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_build_up_enc_param() local
1552 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_enc_param()
1558 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1564 wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1569 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_enc_param()
1570 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_enc_param()
1599 if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) in wave5_vpu_build_up_enc_param()
1920 struct vpu_device *vpu_dev = dev_get_drvdata(dev); in wave5_vpu_enc_register_framebuffer() local
1991 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_mv); in wave5_vpu_enc_register_framebuffer()
2002 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_y_tbl); in wave5_vpu_enc_register_framebuffer()
2010 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_c_tbl); in wave5_vpu_enc_register_framebuffer()
2022 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_sub_sam_buf); in wave5_vpu_enc_register_framebuffer()
2032 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_task); in wave5_vpu_enc_register_framebuffer()
2098 ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); in wave5_vpu_enc_register_framebuffer()
2105 wave5_vdi_free_dma_memory(vpu_dev, &vb_task); in wave5_vpu_enc_register_framebuffer()
2107 wave5_vdi_free_dma_memory(vpu_dev, &vb_sub_sam_buf); in wave5_vpu_enc_register_framebuffer()
2109 wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_c_tbl); in wave5_vpu_enc_register_framebuffer()
2111 wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_y_tbl); in wave5_vpu_enc_register_framebuffer()
2113 wave5_vdi_free_dma_memory(vpu_dev, &vb_mv); in wave5_vpu_enc_register_framebuffer()
2325 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_get_result() local
2381 (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_enc_get_result()
2383 if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) in wave5_vpu_enc_get_result()
2387 vpu_dev->last_performance_cycles = result->enc_encode_end_tick; in wave5_vpu_enc_get_result()
2402 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_check_common_param_valid() local
2403 struct device *dev = vpu_dev->dev; in wave5_vpu_enc_check_common_param_valid()
2523 static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, in wave5_vpu_enc_check_param_valid() argument
2531 dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); in wave5_vpu_enc_check_param_valid()
2532 dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); in wave5_vpu_enc_check_param_valid()
2537 dev_err(vpu_dev->dev, in wave5_vpu_enc_check_param_valid()