Lines Matching refs:p_dec_info
525 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_build_up_dec_param() local
528 p_dec_info->cycle_per_tick = 256; in wave5_vpu_build_up_dec_param()
530 p_dec_info->sec_axi_info.use_bit_enable = 1; in wave5_vpu_build_up_dec_param()
531 p_dec_info->sec_axi_info.use_ip_enable = 1; in wave5_vpu_build_up_dec_param()
532 p_dec_info->sec_axi_info.use_lf_row_enable = 1; in wave5_vpu_build_up_dec_param()
536 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; in wave5_vpu_build_up_dec_param()
539 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; in wave5_vpu_build_up_dec_param()
546 p_dec_info->vb_work.size = WAVE515DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
548 p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
550 ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
557 wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
559 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); in wave5_vpu_build_up_dec_param()
560 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); in wave5_vpu_build_up_dec_param()
567 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); in wave5_vpu_build_up_dec_param()
568 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); in wave5_vpu_build_up_dec_param()
582 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
586 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_dec_param()
593 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_hw_flush_instance() local
611 p_dec_info->instance_queue_count = 0; in wave5_vpu_hw_flush_instance()
612 p_dec_info->report_queue_count = 0; in wave5_vpu_hw_flush_instance()
628 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_init_seq() local
636 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_dec_init_seq()
637 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_init_seq()
639 bs_option = get_bitstream_options(p_dec_info); in wave5_vpu_dec_init_seq()
648 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_dec_init_seq()
654 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_init_seq()
655 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_init_seq()
658 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_init_seq()
667 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_get_dec_seq_result() local
669 p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); in wave5_get_dec_seq_result()
670 info->rd_ptr = p_dec_info->stream_rd_ptr; in wave5_get_dec_seq_result()
672 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_get_dec_seq_result()
714 p_dec_info->vlc_buf_size = info->vlc_buf_size; in wave5_get_dec_seq_result()
715 p_dec_info->param_buf_size = info->param_buf_size; in wave5_get_dec_seq_result()
723 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_seq_info() local
725 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_seq_info()
726 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_seq_info()
736 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_seq_info()
737 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_seq_info()
740 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_seq_info()
757 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_register_framebuffer() local
758 struct dec_initial_info *init_info = &p_dec_info->initial_info; in wave5_vpu_dec_register_framebuffer()
796 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); in wave5_vpu_dec_register_framebuffer()
807 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
812 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
819 vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_dec_register_framebuffer()
820 (p_dec_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); in wave5_vpu_dec_register_framebuffer()
823 if (vb_buf.size != p_dec_info->vb_task.size) { in wave5_vpu_dec_register_framebuffer()
825 &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
831 p_dec_info->vb_task = vb_buf; in wave5_vpu_dec_register_framebuffer()
835 p_dec_info->vb_task.daddr); in wave5_vpu_dec_register_framebuffer()
877 p_dec_info->vb_fbc_y_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
880 p_dec_info->vb_fbc_c_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
882 p_dec_info->vb_mv[idx].daddr); in wave5_vpu_dec_register_framebuffer()
906 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
909 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); in wave5_vpu_dec_register_framebuffer()
912 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); in wave5_vpu_dec_register_framebuffer()
915 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); in wave5_vpu_dec_register_framebuffer()
922 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_validate_sec_axi() local
940 if (p_dec_info->sec_axi_info.use_bit_enable && sram_size >= bit_size) { in wave5_vpu_dec_validate_sec_axi()
945 if (p_dec_info->sec_axi_info.use_ip_enable && sram_size >= ip_size) { in wave5_vpu_dec_validate_sec_axi()
950 if (p_dec_info->sec_axi_info.use_lf_row_enable && sram_size >= lf_size) in wave5_vpu_dec_validate_sec_axi()
959 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_decode() local
962 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_decode()
963 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_decode()
965 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_decode()
972 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_decode()
976 (p_dec_info->target_spatial_id << 9) | in wave5_vpu_decode()
977 (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); in wave5_vpu_decode()
978 vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); in wave5_vpu_decode()
980 vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); in wave5_vpu_decode()
986 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_decode()
987 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_decode()
990 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_decode()
1002 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_result() local
1005 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_result()
1006 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_result()
1016 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_result()
1017 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_result()
1020 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_result()
1072 memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, in wave5_vpu_dec_get_result()
1074 wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); in wave5_vpu_dec_get_result()
1080 if (!p_dec_info->first_cycle_check) { in wave5_vpu_dec_get_result()
1083 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1085 p_dec_info->first_cycle_check = true; in wave5_vpu_dec_get_result()
1089 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1094 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1098 if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) in wave5_vpu_dec_get_result()
1099 p_dec_info->first_cycle_check = false; in wave5_vpu_dec_get_result()
1464 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_set_bitstream_flag() local
1466 p_dec_info->stream_endflag = eos ? 1 : 0; in wave5_vpu_dec_set_bitstream_flag()
1467 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_dec_set_bitstream_flag()
1468 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_set_bitstream_flag()
1475 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_dec_clr_disp_flag() local
1485 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_dec_clr_disp_flag()