Lines Matching +full:msb +full:- +full:justified
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Wave5 series multi-standard codec IP - wave5 backend logic
5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
10 #include "wave5-vpu.h"
12 #include "wave5-regdefine.h"
87 struct device *dev = vpu_dev->dev; in _wave5_print_reg_err()
135 return -ETIMEDOUT; in wave5_wait_fio_readl()
152 dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", in wave5_fio_writel()
160 if (vpu_dev->product_code == WAVE515_CODE) in wave5_wait_bus_busy()
162 if (vpu_dev->product_code == WAVE521C_CODE || in wave5_wait_bus_busy()
163 vpu_dev->product_code == WAVE521_CODE || in wave5_wait_bus_busy()
164 vpu_dev->product_code == WAVE521E1_CODE) in wave5_wait_bus_busy()
203 dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); in wave5_vpu_get_product_id()
206 dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); in wave5_vpu_get_product_id()
219 instance_index = inst->id; in wave5_bit_issue_command()
220 codec_mode = inst->std; in wave5_bit_issue_command()
230 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, in wave5_bit_issue_command()
231 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in wave5_bit_issue_command()
233 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); in wave5_bit_issue_command()
250 * If the fail_res argument is NULL, then just return -EIO. in wave5_vpu_firmware_command_queue_error_check()
257 return -EIO; in wave5_vpu_firmware_command_queue_error_check()
260 return -EBUSY; in wave5_vpu_firmware_command_queue_error_check()
270 wave5_bit_issue_command(inst->dev, inst, cmd); in send_firmware_command()
271 ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); in send_firmware_command()
273 dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__, in send_firmware_command()
274 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in send_firmware_command()
275 return -ETIMEDOUT; in send_firmware_command()
279 *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in send_firmware_command()
287 return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result); in send_firmware_command()
301 dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); in wave5_send_query()
312 if (vpu_dev->attr.support_encoders) { in setup_wave5_interrupts()
319 if (vpu_dev->attr.support_decoders) { in setup_wave5_interrupts()
332 struct vpu_attr *p_attr = &vpu_dev->attr; in setup_wave5_properties()
344 p_attr->product_name[0] = str[3]; in setup_wave5_properties()
345 p_attr->product_name[1] = str[2]; in setup_wave5_properties()
346 p_attr->product_name[2] = str[1]; in setup_wave5_properties()
347 p_attr->product_name[3] = str[0]; in setup_wave5_properties()
348 p_attr->product_name[4] = 0; in setup_wave5_properties()
350 p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); in setup_wave5_properties()
351 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); in setup_wave5_properties()
352 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in setup_wave5_properties()
353 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); in setup_wave5_properties()
358 if (vpu_dev->product_code == WAVE515_CODE) { in setup_wave5_properties()
359 p_attr->support_hevc10bit_dec = FIELD_GET(W515_FEATURE_HEVC10BIT_DEC, in setup_wave5_properties()
361 p_attr->support_decoders = FIELD_GET(W515_FEATURE_HEVC_DECODER, in setup_wave5_properties()
364 p_attr->support_hevc10bit_enc = FIELD_GET(W521_FEATURE_HEVC10BIT_ENC, in setup_wave5_properties()
366 p_attr->support_avc10bit_enc = FIELD_GET(W521_FEATURE_AVC10BIT_ENC, in setup_wave5_properties()
369 p_attr->support_decoders = FIELD_GET(W521_FEATURE_AVC_DECODER, in setup_wave5_properties()
371 p_attr->support_decoders |= FIELD_GET(W521_FEATURE_HEVC_DECODER, in setup_wave5_properties()
373 p_attr->support_encoders = FIELD_GET(W521_FEATURE_AVC_ENCODER, in setup_wave5_properties()
375 p_attr->support_encoders |= FIELD_GET(W521_FEATURE_HEVC_ENCODER, in setup_wave5_properties()
378 p_attr->support_backbone = FIELD_GET(W521_FEATURE_BACKBONE, in setup_wave5_properties()
380 p_attr->support_vcpu_backbone = FIELD_GET(W521_FEATURE_VCPU_BACKBONE, in setup_wave5_properties()
382 p_attr->support_vcore_backbone = FIELD_GET(W521_FEATURE_VCORE_BACKBONE, in setup_wave5_properties()
406 return -EINVAL; in wave5_vpu_get_version()
425 common_vb = &vpu_dev->common_mem; in wave5_vpu_init()
427 code_base = common_vb->daddr; in wave5_vpu_init()
429 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_init()
437 return -EINVAL; in wave5_vpu_init()
444 dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", in wave5_vpu_init()
468 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_init()
487 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_init()
501 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_init()
502 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_init()
510 dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_init()
525 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_build_up_dec_param()
526 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_build_up_dec_param()
528 p_dec_info->cycle_per_tick = 256; in wave5_vpu_build_up_dec_param()
529 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_dec_param()
530 p_dec_info->sec_axi_info.use_bit_enable = 1; in wave5_vpu_build_up_dec_param()
531 p_dec_info->sec_axi_info.use_ip_enable = 1; in wave5_vpu_build_up_dec_param()
532 p_dec_info->sec_axi_info.use_lf_row_enable = 1; in wave5_vpu_build_up_dec_param()
534 switch (inst->std) { in wave5_vpu_build_up_dec_param()
536 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; in wave5_vpu_build_up_dec_param()
539 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; in wave5_vpu_build_up_dec_param()
542 return -EINVAL; in wave5_vpu_build_up_dec_param()
545 if (vpu_dev->product == PRODUCT_ID_515) in wave5_vpu_build_up_dec_param()
546 p_dec_info->vb_work.size = WAVE515DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
548 p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
550 ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
554 if (inst->dev->product_code != WAVE515_CODE) in wave5_vpu_build_up_dec_param()
555 vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); in wave5_vpu_build_up_dec_param()
557 wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
559 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); in wave5_vpu_build_up_dec_param()
560 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); in wave5_vpu_build_up_dec_param()
562 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_build_up_dec_param()
563 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_dec_param()
564 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_dec_param()
567 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); in wave5_vpu_build_up_dec_param()
568 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); in wave5_vpu_build_up_dec_param()
570 /* NOTE: SDMA reads MSB first */ in wave5_vpu_build_up_dec_param()
571 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_build_up_dec_param()
573 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_build_up_dec_param()
575 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_dec_param()
576 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, in wave5_vpu_build_up_dec_param()
577 WAVE521_COMMAND_QUEUE_DEPTH - 1); in wave5_vpu_build_up_dec_param()
582 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
586 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_dec_param()
593 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_hw_flush_instance()
606 dev_warn(inst->dev->dev, in wave5_vpu_hw_flush_instance()
611 p_dec_info->instance_queue_count = 0; in wave5_vpu_hw_flush_instance()
612 p_dec_info->report_queue_count = 0; in wave5_vpu_hw_flush_instance()
621 if (info->stream_endflag) in get_bitstream_options()
628 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_init_seq()
633 if (!inst->codec_info) in wave5_vpu_dec_init_seq()
634 return -EINVAL; in wave5_vpu_dec_init_seq()
636 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_dec_init_seq()
637 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_init_seq()
642 if (inst->dev->product_code == WAVE515_CODE) in wave5_vpu_dec_init_seq()
645 vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); in wave5_vpu_dec_init_seq()
647 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); in wave5_vpu_dec_init_seq()
648 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_dec_init_seq()
654 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_init_seq()
655 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_init_seq()
657 dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__, in wave5_vpu_dec_init_seq()
658 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_init_seq()
667 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_get_dec_seq_result()
669 p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); in wave5_get_dec_seq_result()
670 info->rd_ptr = p_dec_info->stream_rd_ptr; in wave5_get_dec_seq_result()
672 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_get_dec_seq_result()
674 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_get_dec_seq_result()
675 info->pic_width = ((reg_val >> 16) & 0xffff); in wave5_get_dec_seq_result()
676 info->pic_height = (reg_val & 0xffff); in wave5_get_dec_seq_result()
677 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); in wave5_get_dec_seq_result()
679 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); in wave5_get_dec_seq_result()
680 info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
681 info->pic_crop_rect.right = reg_val & 0xffff; in wave5_get_dec_seq_result()
682 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); in wave5_get_dec_seq_result()
683 info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
684 info->pic_crop_rect.bottom = reg_val & 0xffff; in wave5_get_dec_seq_result()
686 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); in wave5_get_dec_seq_result()
687 info->luma_bitdepth = reg_val & 0xf; in wave5_get_dec_seq_result()
688 info->chroma_bitdepth = (reg_val >> 4) & 0xf; in wave5_get_dec_seq_result()
690 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); in wave5_get_dec_seq_result()
692 info->profile = (reg_val >> 24) & 0x1f; in wave5_get_dec_seq_result()
694 if (inst->std == W_HEVC_DEC) { in wave5_get_dec_seq_result()
696 if (!info->profile) { in wave5_get_dec_seq_result()
698 info->profile = HEVC_PROFILE_MAIN; /* main profile */ in wave5_get_dec_seq_result()
700 info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ in wave5_get_dec_seq_result()
703 info->profile = HEVC_PROFILE_STILLPICTURE; in wave5_get_dec_seq_result()
705 info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ in wave5_get_dec_seq_result()
707 } else if (inst->std == W_AVC_DEC) { in wave5_get_dec_seq_result()
708 info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); in wave5_get_dec_seq_result()
711 if (inst->dev->product_code != WAVE515_CODE) { in wave5_get_dec_seq_result()
712 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_get_dec_seq_result()
713 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_get_dec_seq_result()
714 p_dec_info->vlc_buf_size = info->vlc_buf_size; in wave5_get_dec_seq_result()
715 p_dec_info->param_buf_size = info->param_buf_size; in wave5_get_dec_seq_result()
723 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_seq_info()
725 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_seq_info()
726 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_seq_info()
727 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_seq_info()
730 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_dec_get_seq_info()
734 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_seq_info()
736 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_seq_info()
737 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_seq_info()
739 dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_seq_info()
740 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_seq_info()
742 /* this is not a fatal error, set ret to -EIO but don't return immediately */ in wave5_vpu_dec_get_seq_info()
743 if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { in wave5_vpu_dec_get_seq_info()
744 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); in wave5_vpu_dec_get_seq_info()
745 ret = -EIO; in wave5_vpu_dec_get_seq_info()
757 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_register_framebuffer()
758 struct dec_initial_info *init_info = &p_dec_info->initial_info; in wave5_vpu_dec_register_framebuffer()
765 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_dec_register_framebuffer() local
771 cbcr_interleave = inst->cbcr_interleave; in wave5_vpu_dec_register_framebuffer()
772 nv21 = inst->nv21; in wave5_vpu_dec_register_framebuffer()
781 switch (inst->std) { in wave5_vpu_dec_register_framebuffer()
783 mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
784 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
787 mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
788 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
791 return -EINVAL; in wave5_vpu_dec_register_framebuffer()
794 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_register_framebuffer()
796 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); in wave5_vpu_dec_register_framebuffer()
801 frame_width = init_info->pic_width; in wave5_vpu_dec_register_framebuffer()
802 frame_height = init_info->pic_height; in wave5_vpu_dec_register_framebuffer()
807 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
812 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
816 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
818 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_dec_register_framebuffer()
819 vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_dec_register_framebuffer()
820 (p_dec_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); in wave5_vpu_dec_register_framebuffer()
823 if (vb_buf.size != p_dec_info->vb_task.size) { in wave5_vpu_dec_register_framebuffer()
824 wave5_vdi_free_dma_memory(inst->dev, in wave5_vpu_dec_register_framebuffer()
825 &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
826 ret = wave5_vdi_allocate_dma_memory(inst->dev, in wave5_vpu_dec_register_framebuffer()
831 p_dec_info->vb_task = vb_buf; in wave5_vpu_dec_register_framebuffer()
834 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_dec_register_framebuffer()
835 p_dec_info->vb_task.daddr); in wave5_vpu_dec_register_framebuffer()
836 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, in wave5_vpu_dec_register_framebuffer()
840 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
842 if (inst->output_format == FORMAT_422) in wave5_vpu_dec_register_framebuffer()
845 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_dec_register_framebuffer()
849 (justified << 22) | in wave5_vpu_dec_register_framebuffer()
855 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); in wave5_vpu_dec_register_framebuffer()
861 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_dec_register_framebuffer()
862 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_dec_register_framebuffer()
864 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_dec_register_framebuffer()
866 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_dec_register_framebuffer()
872 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); in wave5_vpu_dec_register_framebuffer()
873 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); in wave5_vpu_dec_register_framebuffer()
876 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
877 p_dec_info->vb_fbc_y_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
879 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
880 p_dec_info->vb_fbc_c_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
881 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_dec_register_framebuffer()
882 p_dec_info->vb_mv[idx].daddr); in wave5_vpu_dec_register_framebuffer()
884 vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr); in wave5_vpu_dec_register_framebuffer()
885 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0); in wave5_vpu_dec_register_framebuffer()
886 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0); in wave5_vpu_dec_register_framebuffer()
890 remain -= i; in wave5_vpu_dec_register_framebuffer()
897 reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); in wave5_vpu_dec_register_framebuffer()
899 ret = -EIO; in wave5_vpu_dec_register_framebuffer()
906 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
909 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); in wave5_vpu_dec_register_framebuffer()
912 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); in wave5_vpu_dec_register_framebuffer()
915 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); in wave5_vpu_dec_register_framebuffer()
921 u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth; in wave5_vpu_dec_validate_sec_axi()
922 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_validate_sec_axi()
924 u32 sram_size = inst->dev->sram_size; in wave5_vpu_dec_validate_sec_axi()
925 u32 width = inst->src_fmt.width; in wave5_vpu_dec_validate_sec_axi()
934 if (inst->dev->product_code == WAVE515_CODE) { in wave5_vpu_dec_validate_sec_axi()
940 if (p_dec_info->sec_axi_info.use_bit_enable && sram_size >= bit_size) { in wave5_vpu_dec_validate_sec_axi()
942 sram_size -= bit_size; in wave5_vpu_dec_validate_sec_axi()
945 if (p_dec_info->sec_axi_info.use_ip_enable && sram_size >= ip_size) { in wave5_vpu_dec_validate_sec_axi()
947 sram_size -= ip_size; in wave5_vpu_dec_validate_sec_axi()
950 if (p_dec_info->sec_axi_info.use_lf_row_enable && sram_size >= lf_size) in wave5_vpu_dec_validate_sec_axi()
959 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_decode()
962 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_decode()
963 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_decode()
965 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_decode()
969 vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); in wave5_vpu_decode()
972 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_decode()
974 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL); in wave5_vpu_decode()
975 vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, in wave5_vpu_decode()
976 (p_dec_info->target_spatial_id << 9) | in wave5_vpu_decode()
977 (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); in wave5_vpu_decode()
978 vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); in wave5_vpu_decode()
980 vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); in wave5_vpu_decode()
983 if (ret == -ETIMEDOUT) in wave5_vpu_decode()
986 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_decode()
987 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_decode()
989 dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__, in wave5_vpu_decode()
990 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_decode()
1002 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_result()
1003 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_dec_get_result()
1005 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_result()
1006 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_result()
1007 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_result()
1014 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_result()
1016 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_result()
1017 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_result()
1019 dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_result()
1020 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_result()
1022 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); in wave5_vpu_dec_get_result()
1026 if (inst->std == W_HEVC_DEC) { in wave5_vpu_dec_get_result()
1028 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
1030 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
1032 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
1034 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
1035 if ((nal_unit_type == 19 || nal_unit_type == 20) && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
1037 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
1038 } else if (inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
1040 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
1042 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
1044 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
1046 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
1047 if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
1048 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
1050 index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); in wave5_vpu_dec_get_result()
1051 result->index_frame_display = index; in wave5_vpu_dec_get_result()
1052 index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); in wave5_vpu_dec_get_result()
1053 result->index_frame_decoded = index; in wave5_vpu_dec_get_result()
1054 result->index_frame_decoded_for_tiled = index; in wave5_vpu_dec_get_result()
1056 sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); in wave5_vpu_dec_get_result()
1057 result->temporal_id = sub_layer_info & 0x7; in wave5_vpu_dec_get_result()
1059 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
1060 result->decoded_poc = -1; in wave5_vpu_dec_get_result()
1061 if (result->index_frame_decoded >= 0 || in wave5_vpu_dec_get_result()
1062 result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) in wave5_vpu_dec_get_result()
1063 result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); in wave5_vpu_dec_get_result()
1066 result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); in wave5_vpu_dec_get_result()
1067 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_vpu_dec_get_result()
1068 result->dec_pic_width = reg_val >> 16; in wave5_vpu_dec_get_result()
1069 result->dec_pic_height = reg_val & 0xffff; in wave5_vpu_dec_get_result()
1071 if (result->sequence_changed) { in wave5_vpu_dec_get_result()
1072 memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, in wave5_vpu_dec_get_result()
1074 wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); in wave5_vpu_dec_get_result()
1077 result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); in wave5_vpu_dec_get_result()
1078 result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); in wave5_vpu_dec_get_result()
1080 if (!p_dec_info->first_cycle_check) { in wave5_vpu_dec_get_result()
1081 result->frame_cycle = in wave5_vpu_dec_get_result()
1082 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
1083 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1084 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1085 p_dec_info->first_cycle_check = true; in wave5_vpu_dec_get_result()
1086 } else if (result->index_frame_decoded_for_tiled != -1) { in wave5_vpu_dec_get_result()
1087 result->frame_cycle = in wave5_vpu_dec_get_result()
1088 (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_dec_get_result()
1089 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1090 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1091 if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) in wave5_vpu_dec_get_result()
1092 result->frame_cycle = in wave5_vpu_dec_get_result()
1093 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
1094 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1098 if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) in wave5_vpu_dec_get_result()
1099 p_dec_info->first_cycle_check = false; in wave5_vpu_dec_get_result()
1113 common_vb = &vpu_dev->common_mem; in wave5_vpu_re_init()
1115 code_base = common_vb->daddr; in wave5_vpu_re_init()
1117 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_re_init()
1125 return -EINVAL; in wave5_vpu_re_init()
1137 dev_err(vpu_dev->dev, in wave5_vpu_re_init()
1146 dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); in wave5_vpu_re_init()
1162 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_re_init()
1181 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_re_init()
1199 vpu_dev->sram_buf.daddr); in wave5_vpu_re_init()
1201 vpu_dev->sram_buf.size); in wave5_vpu_re_init()
1210 dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_re_init()
1255 common_vb = &vpu_dev->common_mem; in wave5_vpu_sleep_wake()
1257 code_base = common_vb->daddr; in wave5_vpu_sleep_wake()
1259 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_sleep_wake()
1268 return -EINVAL; in wave5_vpu_sleep_wake()
1287 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_sleep_wake()
1308 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_sleep_wake()
1326 vpu_dev->sram_buf.daddr); in wave5_vpu_sleep_wake()
1328 vpu_dev->sram_buf.size); in wave5_vpu_sleep_wake()
1338 dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_sleep_wake()
1353 struct vpu_attr *p_attr = &vpu_dev->attr; in wave5_vpu_reset()
1365 p_attr->support_backbone = true; in wave5_vpu_reset()
1367 p_attr->support_vcore_backbone = true; in wave5_vpu_reset()
1369 p_attr->support_vcpu_backbone = true; in wave5_vpu_reset()
1372 if (p_attr->support_backbone) { in wave5_vpu_reset()
1375 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1376 if (p_attr->support_vcpu_backbone) { in wave5_vpu_reset()
1394 return -EBUSY; in wave5_vpu_reset()
1403 return -EBUSY; in wave5_vpu_reset()
1426 return -EINVAL; in wave5_vpu_reset()
1440 if (p_attr->support_backbone) { in wave5_vpu_reset()
1441 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1442 if (p_attr->support_vcpu_backbone) in wave5_vpu_reset()
1464 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_set_bitstream_flag()
1466 p_dec_info->stream_endflag = eos ? 1 : 0; in wave5_vpu_dec_set_bitstream_flag()
1467 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_dec_set_bitstream_flag()
1468 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_set_bitstream_flag()
1475 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_dec_clr_disp_flag()
1478 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); in wave5_dec_clr_disp_flag()
1479 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); in wave5_dec_clr_disp_flag()
1481 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_clr_disp_flag()
1485 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_dec_clr_disp_flag()
1494 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); in wave5_dec_set_disp_flag()
1495 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); in wave5_dec_set_disp_flag()
1497 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_set_disp_flag()
1508 interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); in wave5_vpu_clear_interrupt()
1510 vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason); in wave5_vpu_clear_interrupt()
1519 ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1521 return inst->codec_info->dec_info.stream_rd_ptr; in wave5_dec_get_rd_ptr()
1523 return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1530 vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); in wave5_dec_set_rd_ptr()
1532 ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR); in wave5_dec_set_rd_ptr()
1545 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_build_up_enc_param()
1551 p_enc_info->cycle_per_tick = 256; in wave5_vpu_build_up_enc_param()
1552 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_enc_param()
1553 p_enc_info->sec_axi_info.use_enc_rdo_enable = 1; in wave5_vpu_build_up_enc_param()
1554 p_enc_info->sec_axi_info.use_enc_lf_enable = 1; in wave5_vpu_build_up_enc_param()
1557 p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; in wave5_vpu_build_up_enc_param()
1558 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1560 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1564 wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1566 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); in wave5_vpu_build_up_enc_param()
1567 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); in wave5_vpu_build_up_enc_param()
1569 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_enc_param()
1570 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_enc_param()
1572 reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN; in wave5_vpu_build_up_enc_param()
1573 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); in wave5_vpu_build_up_enc_param()
1574 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_enc_param()
1575 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, WAVE521_COMMAND_QUEUE_DEPTH - 1); in wave5_vpu_build_up_enc_param()
1578 vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0); in wave5_vpu_build_up_enc_param()
1579 vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); in wave5_vpu_build_up_enc_param()
1585 buffer_addr = open_param->bitstream_buffer; in wave5_vpu_build_up_enc_param()
1586 buffer_size = open_param->bitstream_buffer_size; in wave5_vpu_build_up_enc_param()
1587 p_enc_info->stream_rd_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1588 p_enc_info->stream_wr_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1589 p_enc_info->line_buf_int_en = open_param->line_buf_int_en; in wave5_vpu_build_up_enc_param()
1590 p_enc_info->stream_buf_start_addr = buffer_addr; in wave5_vpu_build_up_enc_param()
1591 p_enc_info->stream_buf_size = buffer_size; in wave5_vpu_build_up_enc_param()
1592 p_enc_info->stream_buf_end_addr = buffer_addr + buffer_size; in wave5_vpu_build_up_enc_param()
1593 p_enc_info->stride = 0; in wave5_vpu_build_up_enc_param()
1594 p_enc_info->initial_info_obtained = false; in wave5_vpu_build_up_enc_param()
1595 p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_enc_param()
1599 if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) in wave5_vpu_build_up_enc_param()
1600 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1617 pad_right = aligned_width - src_width; in wave5_set_enc_crop_info()
1618 pad_bot = aligned_height - src_height; in wave5_set_enc_crop_info()
1620 if (param->conf_win_right > 0) in wave5_set_enc_crop_info()
1621 crop_right = param->conf_win_right + pad_right; in wave5_set_enc_crop_info()
1625 if (param->conf_win_bot > 0) in wave5_set_enc_crop_info()
1626 crop_bot = param->conf_win_bot + pad_bot; in wave5_set_enc_crop_info()
1630 crop_top = param->conf_win_top; in wave5_set_enc_crop_info()
1631 crop_left = param->conf_win_left; in wave5_set_enc_crop_info()
1633 param->conf_win_top = crop_top; in wave5_set_enc_crop_info()
1634 param->conf_win_left = crop_left; in wave5_set_enc_crop_info()
1635 param->conf_win_bot = crop_bot; in wave5_set_enc_crop_info()
1636 param->conf_win_right = crop_right; in wave5_set_enc_crop_info()
1643 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1644 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1645 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1646 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1650 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1651 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1652 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1653 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1657 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1658 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1659 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1660 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1664 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1665 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1669 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1670 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1674 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1675 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1676 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1677 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1681 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1682 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1683 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1684 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1687 WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode); in wave5_set_enc_crop_info()
1694 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_init_seq()
1695 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_init_seq()
1696 struct enc_wave_param *p_param = &p_open_param->wave_param; in wave5_vpu_enc_init_seq()
1703 if (p_enc_info->rotation_enable) { in wave5_vpu_enc_init_seq()
1704 switch (p_enc_info->rotation_angle) { in wave5_vpu_enc_init_seq()
1720 if (p_enc_info->mirror_enable) { in wave5_vpu_enc_init_seq()
1721 switch (p_enc_info->mirror_direction) { in wave5_vpu_enc_init_seq()
1737 wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width, in wave5_vpu_enc_init_seq()
1738 p_open_param->pic_height); in wave5_vpu_enc_init_seq()
1741 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON); in wave5_vpu_enc_init_seq()
1742 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16 in wave5_vpu_enc_init_seq()
1743 | p_open_param->pic_width); in wave5_vpu_enc_init_seq()
1744 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); in wave5_vpu_enc_init_seq()
1746 reg_val = p_param->profile | in wave5_vpu_enc_init_seq()
1747 (p_param->level << 3) | in wave5_vpu_enc_init_seq()
1748 (p_param->internal_bit_depth << 14); in wave5_vpu_enc_init_seq()
1749 if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1750 reg_val |= (p_param->tier << 12) | in wave5_vpu_enc_init_seq()
1751 (p_param->tmvp_enable << 23) | in wave5_vpu_enc_init_seq()
1752 (p_param->sao_enable << 24) | in wave5_vpu_enc_init_seq()
1753 (p_param->skip_intra_trans << 25) | in wave5_vpu_enc_init_seq()
1754 (p_param->strong_intra_smooth_enable << 27) | in wave5_vpu_enc_init_seq()
1755 (p_param->en_still_picture << 30); in wave5_vpu_enc_init_seq()
1756 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1758 reg_val = (p_param->lossless_enable) | in wave5_vpu_enc_init_seq()
1759 (p_param->const_intra_pred_flag << 1) | in wave5_vpu_enc_init_seq()
1760 (p_param->lf_cross_slice_boundary_enable << 2) | in wave5_vpu_enc_init_seq()
1761 (p_param->wpp_enable << 4) | in wave5_vpu_enc_init_seq()
1762 (p_param->disable_deblk << 5) | in wave5_vpu_enc_init_seq()
1763 ((p_param->beta_offset_div2 & 0xF) << 6) | in wave5_vpu_enc_init_seq()
1764 ((p_param->tc_offset_div2 & 0xF) << 10) | in wave5_vpu_enc_init_seq()
1765 ((p_param->chroma_cb_qp_offset & 0x1F) << 14) | in wave5_vpu_enc_init_seq()
1766 ((p_param->chroma_cr_qp_offset & 0x1F) << 19) | in wave5_vpu_enc_init_seq()
1767 (p_param->transform8x8_enable << 29) | in wave5_vpu_enc_init_seq()
1768 (p_param->entropy_coding_mode << 30); in wave5_vpu_enc_init_seq()
1769 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1771 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx); in wave5_vpu_enc_init_seq()
1773 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1774 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | in wave5_vpu_enc_init_seq()
1775 ((p_param->intra_period & 0x7ff) << 6) | in wave5_vpu_enc_init_seq()
1776 ((p_param->avc_idr_period & 0x7ff) << 17)); in wave5_vpu_enc_init_seq()
1777 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1778 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, in wave5_vpu_enc_init_seq()
1779 p_param->decoding_refresh_type | (p_param->intra_qp << 3) | in wave5_vpu_enc_init_seq()
1780 (p_param->intra_period << 16)); in wave5_vpu_enc_init_seq()
1782 reg_val = (p_param->rdo_skip << 2) | in wave5_vpu_enc_init_seq()
1783 (p_param->lambda_scaling_enable << 3) | in wave5_vpu_enc_init_seq()
1785 (p_param->intra_nx_n_enable << 8) | in wave5_vpu_enc_init_seq()
1786 (p_param->max_num_merge << 18); in wave5_vpu_enc_init_seq()
1788 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1790 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1791 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1792 p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); in wave5_vpu_enc_init_seq()
1793 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1794 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1795 p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); in wave5_vpu_enc_init_seq()
1797 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); in wave5_vpu_enc_init_seq()
1798 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); in wave5_vpu_enc_init_seq()
1800 reg_val = p_open_param->rc_enable | in wave5_vpu_enc_init_seq()
1801 (p_param->hvs_qp_enable << 2) | in wave5_vpu_enc_init_seq()
1802 (p_param->hvs_qp_scale << 4) | in wave5_vpu_enc_init_seq()
1803 ((p_param->initial_rc_qp & 0x3F) << 14) | in wave5_vpu_enc_init_seq()
1804 (p_open_param->vbv_buffer_size << 20); in wave5_vpu_enc_init_seq()
1805 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1806 reg_val |= (p_param->mb_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1807 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1808 reg_val |= (p_param->cu_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1809 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1811 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, in wave5_vpu_enc_init_seq()
1812 p_param->rc_weight_buf << 8 | p_param->rc_weight_param); in wave5_vpu_enc_init_seq()
1814 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i | in wave5_vpu_enc_init_seq()
1815 (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12)); in wave5_vpu_enc_init_seq()
1817 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p | in wave5_vpu_enc_init_seq()
1818 (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | in wave5_vpu_enc_init_seq()
1819 (p_param->max_qp_b << 18)); in wave5_vpu_enc_init_seq()
1821 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0); in wave5_vpu_enc_init_seq()
1822 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0); in wave5_vpu_enc_init_seq()
1823 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); in wave5_vpu_enc_init_seq()
1825 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0); in wave5_vpu_enc_init_seq()
1826 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0); in wave5_vpu_enc_init_seq()
1827 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, in wave5_vpu_enc_init_seq()
1828 p_param->conf_win_bot << 16 | p_param->conf_win_top); in wave5_vpu_enc_init_seq()
1829 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, in wave5_vpu_enc_init_seq()
1830 p_param->conf_win_right << 16 | p_param->conf_win_left); in wave5_vpu_enc_init_seq()
1832 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1833 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1834 p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); in wave5_vpu_enc_init_seq()
1835 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1836 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1837 p_param->independ_slice_mode_arg << 16 | in wave5_vpu_enc_init_seq()
1838 p_param->independ_slice_mode); in wave5_vpu_enc_init_seq()
1840 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0); in wave5_vpu_enc_init_seq()
1841 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0); in wave5_vpu_enc_init_seq()
1842 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0); in wave5_vpu_enc_init_seq()
1843 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0); in wave5_vpu_enc_init_seq()
1845 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_init_seq()
1846 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0); in wave5_vpu_enc_init_seq()
1847 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0); in wave5_vpu_enc_init_seq()
1848 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0); in wave5_vpu_enc_init_seq()
1849 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0); in wave5_vpu_enc_init_seq()
1850 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0); in wave5_vpu_enc_init_seq()
1851 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0); in wave5_vpu_enc_init_seq()
1852 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0); in wave5_vpu_enc_init_seq()
1853 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1854 p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); in wave5_vpu_enc_init_seq()
1856 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0); in wave5_vpu_enc_init_seq()
1858 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, in wave5_vpu_enc_init_seq()
1859 p_param->nr_intra_weight_y | in wave5_vpu_enc_init_seq()
1860 (p_param->nr_intra_weight_cb << 5) | in wave5_vpu_enc_init_seq()
1861 (p_param->nr_intra_weight_cr << 10) | in wave5_vpu_enc_init_seq()
1862 (p_param->nr_inter_weight_y << 15) | in wave5_vpu_enc_init_seq()
1863 (p_param->nr_inter_weight_cb << 20) | in wave5_vpu_enc_init_seq()
1864 (p_param->nr_inter_weight_cr << 25)); in wave5_vpu_enc_init_seq()
1866 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); in wave5_vpu_enc_init_seq()
1875 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_seq_info()
1878 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_seq_info()
1882 dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); in wave5_vpu_enc_get_seq_info()
1884 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_seq_info()
1886 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_seq_info()
1887 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_seq_info()
1889 if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { in wave5_vpu_enc_get_seq_info()
1890 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_seq_info()
1891 ret = -EIO; in wave5_vpu_enc_get_seq_info()
1893 info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_seq_info()
1896 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); in wave5_vpu_enc_get_seq_info()
1897 info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); in wave5_vpu_enc_get_seq_info()
1898 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1899 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1900 p_enc_info->vlc_buf_size = info->vlc_buf_size; in wave5_vpu_enc_get_seq_info()
1901 p_enc_info->param_buf_size = info->param_buf_size; in wave5_vpu_enc_get_seq_info()
1930 bool avc_encoding = (inst->std == W_AVC_ENC); in wave5_vpu_enc_register_framebuffer()
1937 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_register_framebuffer()
1939 p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_register_framebuffer()
1943 stride = p_enc_info->stride; in wave5_vpu_enc_register_framebuffer()
1944 bit_depth = p_open_param->wave_param.internal_bit_depth; in wave5_vpu_enc_register_framebuffer()
1947 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1948 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1950 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1951 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1952 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1953 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1954 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1957 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1958 buf_width = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1959 buf_height = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1962 buf_width = ALIGN(p_open_param->pic_width, 8); in wave5_vpu_enc_register_framebuffer()
1963 buf_height = ALIGN(p_open_param->pic_height, 8); in wave5_vpu_enc_register_framebuffer()
1965 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1966 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1967 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1968 buf_width = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
1969 buf_height = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1972 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1973 buf_width = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1974 buf_height = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
1995 p_enc_info->vb_mv = vb_mv; in wave5_vpu_enc_register_framebuffer()
2006 p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; in wave5_vpu_enc_register_framebuffer()
2014 p_enc_info->vb_fbc_c_tbl = vb_fbc_c_tbl; in wave5_vpu_enc_register_framebuffer()
2026 p_enc_info->vb_sub_sam_buf = vb_sub_sam_buf; in wave5_vpu_enc_register_framebuffer()
2028 vb_task.size = (p_enc_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_enc_register_framebuffer()
2029 (p_enc_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); in wave5_vpu_enc_register_framebuffer()
2031 if (p_enc_info->vb_task.size == 0) { in wave5_vpu_enc_register_framebuffer()
2036 p_enc_info->vb_task = vb_task; in wave5_vpu_enc_register_framebuffer()
2038 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_enc_register_framebuffer()
2039 p_enc_info->vb_task.daddr); in wave5_vpu_enc_register_framebuffer()
2040 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); in wave5_vpu_enc_register_framebuffer()
2043 /* set sub-sampled buffer base addr */ in wave5_vpu_enc_register_framebuffer()
2044 vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); in wave5_vpu_enc_register_framebuffer()
2045 /* set sub-sampled buffer size for one frame */ in wave5_vpu_enc_register_framebuffer()
2046 vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); in wave5_vpu_enc_register_framebuffer()
2048 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_enc_register_framebuffer()
2051 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
2052 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
2053 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
2057 luma_stride = calculate_luma_stride(p_open_param->pic_width, bit_depth); in wave5_vpu_enc_register_framebuffer()
2058 chroma_stride = calculate_chroma_stride(p_open_param->pic_width / 2, bit_depth); in wave5_vpu_enc_register_framebuffer()
2061 vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride); in wave5_vpu_enc_register_framebuffer()
2062 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); in wave5_vpu_enc_register_framebuffer()
2068 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_enc_register_framebuffer()
2069 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_enc_register_framebuffer()
2071 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_enc_register_framebuffer()
2073 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_enc_register_framebuffer()
2076 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i + in wave5_vpu_enc_register_framebuffer()
2078 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2081 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2084 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2087 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_enc_register_framebuffer()
2091 remain -= i; in wave5_vpu_enc_register_framebuffer()
2119 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_validate_sec_axi()
2121 u32 sram_size = inst->dev->sram_size; in wave5_vpu_enc_validate_sec_axi()
2127 * TODO: calculate rdo_size and lf_size from inst->src_fmt.width and in wave5_vpu_enc_validate_sec_axi()
2128 * inst->codec_info->enc_info.open_param.wave_param.internal_bit_depth in wave5_vpu_enc_validate_sec_axi()
2131 if (p_enc_info->sec_axi_info.use_enc_rdo_enable && sram_size >= rdo_size) { in wave5_vpu_enc_validate_sec_axi()
2133 sram_size -= rdo_size; in wave5_vpu_enc_validate_sec_axi()
2136 if (p_enc_info->sec_axi_info.use_enc_lf_enable && sram_size >= lf_size) in wave5_vpu_enc_validate_sec_axi()
2147 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_encode()
2148 struct frame_buffer *p_src_frame = option->source_frame; in wave5_vpu_encode()
2149 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_encode()
2150 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode() local
2154 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); in wave5_vpu_encode()
2155 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); in wave5_vpu_encode()
2156 p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; in wave5_vpu_encode()
2157 p_enc_info->stream_buf_size = option->pic_stream_buffer_size; in wave5_vpu_encode()
2158 p_enc_info->stream_buf_end_addr = in wave5_vpu_encode()
2159 option->pic_stream_buffer_addr + option->pic_stream_buffer_size; in wave5_vpu_encode()
2161 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); in wave5_vpu_encode()
2164 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); in wave5_vpu_encode()
2166 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); in wave5_vpu_encode()
2172 if (option->code_option.implicit_header_encode) in wave5_vpu_encode()
2173 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
2175 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
2176 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
2177 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
2179 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
2180 option->code_option.implicit_header_encode | in wave5_vpu_encode()
2181 (option->code_option.encode_vcl << 1) | in wave5_vpu_encode()
2182 (option->code_option.encode_vps << 2) | in wave5_vpu_encode()
2183 (option->code_option.encode_sps << 3) | in wave5_vpu_encode()
2184 (option->code_option.encode_pps << 4) | in wave5_vpu_encode()
2185 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
2186 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
2187 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
2189 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0); in wave5_vpu_encode()
2191 if (option->src_end_flag) in wave5_vpu_encode()
2193 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); in wave5_vpu_encode()
2195 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); in wave5_vpu_encode()
2197 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); in wave5_vpu_encode()
2198 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); in wave5_vpu_encode()
2199 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); in wave5_vpu_encode()
2201 switch (p_open_param->src_format) { in wave5_vpu_encode()
2208 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2210 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2211 (p_src_frame->stride / 2); in wave5_vpu_encode()
2212 src_stride_c = (p_open_param->src_format == FORMAT_422) ? src_stride_c * 2 : in wave5_vpu_encode()
2221 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2223 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2224 (p_src_frame->stride / 2); in wave5_vpu_encode()
2225 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2234 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2236 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2237 (p_src_frame->stride / 2); in wave5_vpu_encode()
2238 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2247 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2249 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2250 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2251 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2260 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2262 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2263 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2264 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2268 return -EINVAL; in wave5_vpu_encode()
2271 src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21); in wave5_vpu_encode()
2272 switch (p_open_param->packed_format) { in wave5_vpu_encode()
2289 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, in wave5_vpu_encode()
2290 (p_src_frame->stride << 16) | src_stride_c); in wave5_vpu_encode()
2291 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | in wave5_vpu_encode()
2292 (format_no << 3) | (justified << 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN << 6)); in wave5_vpu_encode()
2294 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0); in wave5_vpu_encode()
2295 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0); in wave5_vpu_encode()
2296 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0); in wave5_vpu_encode()
2297 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0); in wave5_vpu_encode()
2298 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0); in wave5_vpu_encode()
2299 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0); in wave5_vpu_encode()
2300 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0); in wave5_vpu_encode()
2301 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); in wave5_vpu_encode()
2302 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2303 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); in wave5_vpu_encode()
2304 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2307 if (ret == -ETIMEDOUT) in wave5_vpu_encode()
2310 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_encode()
2311 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_encode()
2324 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_result()
2325 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_get_result()
2327 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_result()
2331 dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); in wave5_vpu_enc_get_result()
2333 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_result()
2335 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_result()
2336 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_result()
2338 encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); in wave5_vpu_enc_get_result()
2340 result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_result()
2341 return -EIO; in wave5_vpu_enc_get_result()
2344 result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_result()
2346 reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); in wave5_vpu_enc_get_result()
2347 result->pic_type = reg_val & 0xFFFF; in wave5_vpu_enc_get_result()
2349 result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); in wave5_vpu_enc_get_result()
2352 * inst->frame_buf in wave5_vpu_enc_get_result()
2354 result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); in wave5_vpu_enc_get_result()
2355 result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); in wave5_vpu_enc_get_result()
2356 result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); in wave5_vpu_enc_get_result()
2357 p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); in wave5_vpu_enc_get_result()
2358 p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2360 result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2361 result->rd_ptr = p_enc_info->stream_rd_ptr; in wave5_vpu_enc_get_result()
2362 result->wr_ptr = p_enc_info->stream_wr_ptr; in wave5_vpu_enc_get_result()
2365 if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) in wave5_vpu_enc_get_result()
2366 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2367 else if (result->recon_frame_index < 0) in wave5_vpu_enc_get_result()
2368 result->bitstream_size = 0; in wave5_vpu_enc_get_result()
2370 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2372 result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); in wave5_vpu_enc_get_result()
2373 result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); in wave5_vpu_enc_get_result()
2375 if (!p_enc_info->first_cycle_check) { in wave5_vpu_enc_get_result()
2376 result->frame_cycle = (result->enc_encode_end_tick - result->enc_host_cmd_tick) * in wave5_vpu_enc_get_result()
2377 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2378 p_enc_info->first_cycle_check = true; in wave5_vpu_enc_get_result()
2380 result->frame_cycle = in wave5_vpu_enc_get_result()
2381 (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_enc_get_result()
2382 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2383 if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) in wave5_vpu_enc_get_result()
2384 result->frame_cycle = (result->enc_encode_end_tick - in wave5_vpu_enc_get_result()
2385 result->enc_host_cmd_tick) * p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2387 vpu_dev->last_performance_cycles = result->enc_encode_end_tick; in wave5_vpu_enc_get_result()
2401 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_common_param_valid()
2402 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_check_common_param_valid()
2403 struct device *dev = vpu_dev->dev; in wave5_vpu_enc_check_common_param_valid()
2404 u32 num_ctu_row = (open_param->pic_height + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2405 u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2408 if (inst->std == W_HEVC_ENC && low_delay && in wave5_vpu_enc_check_common_param_valid()
2409 param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { in wave5_vpu_enc_check_common_param_valid()
2413 param->decoding_refresh_type = 2; in wave5_vpu_enc_check_common_param_valid()
2416 if (param->wpp_enable && param->independ_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2417 unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; in wave5_vpu_enc_check_common_param_valid()
2419 if (param->independ_slice_mode_arg % num_ctb_in_width) { in wave5_vpu_enc_check_common_param_valid()
2421 param->independ_slice_mode_arg, num_ctb_in_width); in wave5_vpu_enc_check_common_param_valid()
2426 /* multi-slice & wpp */ in wave5_vpu_enc_check_common_param_valid()
2427 if (param->wpp_enable && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2432 if (!param->independ_slice_mode && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2435 } else if (param->independ_slice_mode && in wave5_vpu_enc_check_common_param_valid()
2436 param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && in wave5_vpu_enc_check_common_param_valid()
2437 param->independ_slice_mode_arg < param->depend_slice_mode_arg) { in wave5_vpu_enc_check_common_param_valid()
2439 param->independ_slice_mode_arg, param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2443 if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2445 param->independ_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2449 if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2451 param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2455 if (param->conf_win_top % 2) { in wave5_vpu_enc_check_common_param_valid()
2456 dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); in wave5_vpu_enc_check_common_param_valid()
2460 if (param->conf_win_bot % 2) { in wave5_vpu_enc_check_common_param_valid()
2461 dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); in wave5_vpu_enc_check_common_param_valid()
2465 if (param->conf_win_left % 2) { in wave5_vpu_enc_check_common_param_valid()
2466 dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); in wave5_vpu_enc_check_common_param_valid()
2470 if (param->conf_win_right % 2) { in wave5_vpu_enc_check_common_param_valid()
2472 param->conf_win_right); in wave5_vpu_enc_check_common_param_valid()
2476 if (param->lossless_enable && open_param->rc_enable) { in wave5_vpu_enc_check_common_param_valid()
2481 if (param->lossless_enable && !param->skip_intra_trans) { in wave5_vpu_enc_check_common_param_valid()
2487 if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { in wave5_vpu_enc_check_common_param_valid()
2489 param->intra_refresh_mode, param->intra_refresh_arg); in wave5_vpu_enc_check_common_param_valid()
2492 switch (param->intra_refresh_mode) { in wave5_vpu_enc_check_common_param_valid()
2494 if (param->intra_mb_refresh_arg > num_ctu_row) in wave5_vpu_enc_check_common_param_valid()
2498 if (param->intra_refresh_arg > num_ctu_col) in wave5_vpu_enc_check_common_param_valid()
2502 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2506 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2508 if (param->lossless_enable) { in wave5_vpu_enc_check_common_param_valid()
2510 param->intra_refresh_mode); in wave5_vpu_enc_check_common_param_valid()
2518 param->intra_refresh_mode, param->intra_refresh_arg, in wave5_vpu_enc_check_common_param_valid()
2526 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_param_valid()
2528 if (open_param->rc_enable) { in wave5_vpu_enc_check_param_valid()
2529 if (param->min_qp_i > param->max_qp_i || param->min_qp_p > param->max_qp_p || in wave5_vpu_enc_check_param_valid()
2530 param->min_qp_b > param->max_qp_b) { in wave5_vpu_enc_check_param_valid()
2531 dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); in wave5_vpu_enc_check_param_valid()
2532 dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); in wave5_vpu_enc_check_param_valid()
2536 if (open_param->bit_rate <= (int)open_param->frame_rate_info) { in wave5_vpu_enc_check_param_valid()
2537 dev_err(vpu_dev->dev, in wave5_vpu_enc_check_param_valid()
2539 open_param->bit_rate, (int)open_param->frame_rate_info); in wave5_vpu_enc_check_param_valid()
2551 s32 product_id = inst->dev->product; in wave5_vpu_enc_check_open_param()
2552 struct vpu_attr *p_attr = &inst->dev->attr; in wave5_vpu_enc_check_open_param()
2556 return -EINVAL; in wave5_vpu_enc_check_open_param()
2558 param = &open_param->wave_param; in wave5_vpu_enc_check_open_param()
2559 pic_width = open_param->pic_width; in wave5_vpu_enc_check_open_param()
2560 pic_height = open_param->pic_height; in wave5_vpu_enc_check_open_param()
2562 if (inst->id >= MAX_NUM_INSTANCE) { in wave5_vpu_enc_check_open_param()
2563 dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", in wave5_vpu_enc_check_open_param()
2564 inst->id, MAX_NUM_INSTANCE); in wave5_vpu_enc_check_open_param()
2565 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2568 if (inst->std != W_HEVC_ENC && in wave5_vpu_enc_check_open_param()
2569 !(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) { in wave5_vpu_enc_check_open_param()
2570 dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n"); in wave5_vpu_enc_check_open_param()
2571 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2574 if (param->internal_bit_depth == 10) { in wave5_vpu_enc_check_open_param()
2575 if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) { in wave5_vpu_enc_check_open_param()
2576 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2578 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2579 } else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) { in wave5_vpu_enc_check_open_param()
2580 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2582 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2586 if (!open_param->frame_rate_info) { in wave5_vpu_enc_check_open_param()
2587 dev_err(inst->dev->dev, "No frame rate information.\n"); in wave5_vpu_enc_check_open_param()
2588 return -EINVAL; in wave5_vpu_enc_check_open_param()
2591 if (open_param->bit_rate > MAX_BIT_RATE) { in wave5_vpu_enc_check_open_param()
2592 dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2593 open_param->bit_rate, MAX_BIT_RATE); in wave5_vpu_enc_check_open_param()
2594 return -EINVAL; in wave5_vpu_enc_check_open_param()
2599 dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n", in wave5_vpu_enc_check_open_param()
2601 return -EINVAL; in wave5_vpu_enc_check_open_param()
2604 if (param->profile) { in wave5_vpu_enc_check_open_param()
2605 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2606 if ((param->profile != HEVC_PROFILE_MAIN || in wave5_vpu_enc_check_open_param()
2607 (param->profile == HEVC_PROFILE_MAIN && in wave5_vpu_enc_check_open_param()
2608 param->internal_bit_depth > 8)) && in wave5_vpu_enc_check_open_param()
2609 (param->profile != HEVC_PROFILE_MAIN10 || in wave5_vpu_enc_check_open_param()
2610 (param->profile == HEVC_PROFILE_MAIN10 && in wave5_vpu_enc_check_open_param()
2611 param->internal_bit_depth < 10)) && in wave5_vpu_enc_check_open_param()
2612 param->profile != HEVC_PROFILE_STILLPICTURE) { in wave5_vpu_enc_check_open_param()
2613 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2614 "Invalid HEVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2615 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2616 return -EINVAL; in wave5_vpu_enc_check_open_param()
2618 } else if (inst->std == W_AVC_ENC) { in wave5_vpu_enc_check_open_param()
2619 if ((param->internal_bit_depth > 8 && in wave5_vpu_enc_check_open_param()
2620 param->profile != H264_PROFILE_HIGH10)) { in wave5_vpu_enc_check_open_param()
2621 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2622 "Invalid AVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2623 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2624 return -EINVAL; in wave5_vpu_enc_check_open_param()
2629 if (param->decoding_refresh_type > DEC_REFRESH_TYPE_IDR) { in wave5_vpu_enc_check_open_param()
2630 dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n", in wave5_vpu_enc_check_open_param()
2631 param->decoding_refresh_type); in wave5_vpu_enc_check_open_param()
2632 return -EINVAL; in wave5_vpu_enc_check_open_param()
2635 if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { in wave5_vpu_enc_check_open_param()
2636 dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", in wave5_vpu_enc_check_open_param()
2637 param->intra_refresh_mode); in wave5_vpu_enc_check_open_param()
2638 return -EINVAL; in wave5_vpu_enc_check_open_param()
2641 if (inst->std == W_HEVC_ENC && param->independ_slice_mode && in wave5_vpu_enc_check_open_param()
2642 param->depend_slice_mode > DEPEND_SLICE_MODE_BOOST) { in wave5_vpu_enc_check_open_param()
2643 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2645 return -EINVAL; in wave5_vpu_enc_check_open_param()
2648 if (!param->disable_deblk) { in wave5_vpu_enc_check_open_param()
2649 if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2650 dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2651 param->beta_offset_div2); in wave5_vpu_enc_check_open_param()
2652 return -EINVAL; in wave5_vpu_enc_check_open_param()
2655 if (param->tc_offset_div2 < -6 || param->tc_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2656 dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2657 param->tc_offset_div2); in wave5_vpu_enc_check_open_param()
2658 return -EINVAL; in wave5_vpu_enc_check_open_param()
2662 if (param->intra_qp > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2663 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2664 "Invalid intra quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2665 param->intra_qp, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2666 return -EINVAL; in wave5_vpu_enc_check_open_param()
2669 if (open_param->rc_enable) { in wave5_vpu_enc_check_open_param()
2670 if (param->min_qp_i > MAX_INTRA_QP || param->max_qp_i > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2671 param->min_qp_p > MAX_INTRA_QP || param->max_qp_p > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2672 param->min_qp_b > MAX_INTRA_QP || param->max_qp_b > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2673 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2675 "I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2676 param->min_qp_i, param->max_qp_i, param->min_qp_p, param->max_qp_p, in wave5_vpu_enc_check_open_param()
2677 param->min_qp_b, param->max_qp_b, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2678 return -EINVAL; in wave5_vpu_enc_check_open_param()
2681 if (param->hvs_qp_enable && param->hvs_max_delta_qp > MAX_HVS_MAX_DELTA_QP) { in wave5_vpu_enc_check_open_param()
2682 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2683 "Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2684 param->hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP); in wave5_vpu_enc_check_open_param()
2685 return -EINVAL; in wave5_vpu_enc_check_open_param()
2688 if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || in wave5_vpu_enc_check_open_param()
2689 open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { in wave5_vpu_enc_check_open_param()
2690 dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", in wave5_vpu_enc_check_open_param()
2691 open_param->vbv_buffer_size, MIN_VBV_BUFFER_SIZE, in wave5_vpu_enc_check_open_param()
2693 return -EINVAL; in wave5_vpu_enc_check_open_param()
2698 return -EINVAL; in wave5_vpu_enc_check_open_param()
2700 if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param)) in wave5_vpu_enc_check_open_param()
2701 return -EINVAL; in wave5_vpu_enc_check_open_param()
2703 if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2704 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2705 "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2706 param->chroma_cb_qp_offset); in wave5_vpu_enc_check_open_param()
2707 return -EINVAL; in wave5_vpu_enc_check_open_param()
2710 if (param->chroma_cr_qp_offset < -12 || param->chroma_cr_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2711 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2712 "Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2713 param->chroma_cr_qp_offset); in wave5_vpu_enc_check_open_param()
2714 return -EINVAL; in wave5_vpu_enc_check_open_param()
2717 if (param->intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE && !param->intra_refresh_arg) { in wave5_vpu_enc_check_open_param()
2718 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2719 "Intra refresh mode CTU step-size requires an argument\n"); in wave5_vpu_enc_check_open_param()
2720 return -EINVAL; in wave5_vpu_enc_check_open_param()
2723 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2724 if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2725 param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2726 param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { in wave5_vpu_enc_check_open_param()
2727 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2729 param->nr_intra_weight_y, param->nr_intra_weight_cb, in wave5_vpu_enc_check_open_param()
2730 param->nr_intra_weight_cr, MAX_INTRA_WEIGHT); in wave5_vpu_enc_check_open_param()
2731 return -EINVAL; in wave5_vpu_enc_check_open_param()
2734 if (param->nr_inter_weight_y > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2735 param->nr_inter_weight_cb > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2736 param->nr_inter_weight_cr > MAX_INTER_WEIGHT) { in wave5_vpu_enc_check_open_param()
2737 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2739 param->nr_inter_weight_y, param->nr_inter_weight_cb, in wave5_vpu_enc_check_open_param()
2740 param->nr_inter_weight_cr, MAX_INTER_WEIGHT); in wave5_vpu_enc_check_open_param()
2741 return -EINVAL; in wave5_vpu_enc_check_open_param()