88 	u32 reg_val;  in _wave5_print_reg_err()  local
310 	u32 reg_val = 0;  in setup_wave5_interrupts()  local
333 	u32 reg_val;  in setup_wave5_properties()  local
393 	u32 reg_val;  in wave5_vpu_get_version()  local
421 	u32 i, reg_val, reason_code;  in wave5_vpu_init()  local
595 	u32 reg_val = 0;  in wave5_vpu_hw_flush_instance()  local
630 	u32 reg_val, fail_res;  in wave5_vpu_dec_init_seq()  local
665 	u32 reg_val;  in wave5_get_dec_seq_result()  local
722 	u32 reg_val;  in wave5_vpu_dec_get_seq_info()  local
761 	u32 reg_val, cbcr_interleave, nv21, pic_size;  in wave5_vpu_dec_register_framebuffer()  local
958 	u32 reg_val;  in wave5_vpu_decode()  local
1001 	u32 index, nal_unit_type, reg_val, sub_layer_info;  in wave5_vpu_dec_get_result()  local
1110 	u32 reg_val;  in wave5_vpu_re_init()  local
1225 	u32 reg_val;  in wave5_vpu_sleep_wake()  local
1546 	u32 reg_val;  in wave5_vpu_build_up_enc_param()  local
1693 	u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7;  in wave5_vpu_enc_init_seq()  local
1874 	u32 reg_val;  in wave5_vpu_enc_get_seq_info()  local
1925 	u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size;  in wave5_vpu_enc_register_framebuffer()  local
2145 	u32 reg_val = 0;  in wave5_vpu_encode()  local
2323 	u32 reg_val;  in wave5_vpu_enc_get_result()  local