20 #define IMX8Q_CSR_CM0Px_ADDR_OFFSET			0x00000000
21 #define IMX8Q_CSR_CM0Px_CPUWAIT				0x00000004
27 #define VPU_DISABLE_BITS			0x7
29 #define VPU_ENCODER_MASK			0x1
30 #define VPU_DECODER_MASK			0x3UL
31 #define VPU_DECODER_H264_MASK			0x2UL
32 #define VPU_DECODER_HEVC_MASK			0x1UL
46 	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f);  in vpu_imx8q_setup_dec()
47 	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff);  in vpu_imx8q_setup_dec()
49 	return 0;  in vpu_imx8q_setup_dec()
54 	return 0;  in vpu_imx8q_setup_enc()
61 	vpu_readl(vpu, offset + 0x108);  in vpu_imx8q_setup()
63 	vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1);  in vpu_imx8q_setup()
64 	vpu_writel(vpu, offset + 0x190, 0xffffffff);  in vpu_imx8q_setup()
65 	vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff);  in vpu_imx8q_setup()
66 	vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE);  in vpu_imx8q_setup()
67 	vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7);  in vpu_imx8q_setup()
68 	vpu_writel(vpu, XMEM_CONTROL, 0x102);  in vpu_imx8q_setup()
70 	vpu_readl(vpu, offset + 0x108);  in vpu_imx8q_setup()
72 	return 0;  in vpu_imx8q_setup()
77 	return 0;  in vpu_imx8q_reset_enc()
84 	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff);  in vpu_imx8q_reset_dec()
86 	return 0;  in vpu_imx8q_reset_dec()
93 	vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7);  in vpu_imx8q_reset()
97 	return 0;  in vpu_imx8q_reset()
106 	case 0:  in vpu_imx8q_set_system_cfg_common()
107 		config->malone_base_addr[0] = regs + DEC_MFD_XREG_SLV_BASE;  in vpu_imx8q_set_system_cfg_common()
109 		config->num_windsors = 0;  in vpu_imx8q_set_system_cfg_common()
112 		config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_0_BASE;  in vpu_imx8q_set_system_cfg_common()
114 		config->num_malones = 0;  in vpu_imx8q_set_system_cfg_common()
117 		config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_1_BASE;  in vpu_imx8q_set_system_cfg_common()
119 		config->num_malones = 0;  in vpu_imx8q_set_system_cfg_common()
125 		config->windsor_irq_pin[0x0][0x0] = WINDSOR_PAL_IRQ_PIN_L;  in vpu_imx8q_set_system_cfg_common()
126 		config->windsor_irq_pin[0x0][0x1] = WINDSOR_PAL_IRQ_PIN_H;  in vpu_imx8q_set_system_cfg_common()
129 	config->malone_base_addr[0x1] = 0x0;  in vpu_imx8q_set_system_cfg_common()
130 	config->hif_offset[0x0] = MFD_HIF;  in vpu_imx8q_set_system_cfg_common()
131 	config->hif_offset[0x1] = 0x0;  in vpu_imx8q_set_system_cfg_common()
133 	config->dpv_base_addr = 0x0;  in vpu_imx8q_set_system_cfg_common()
134 	config->dpv_irq_pin = 0x0;  in vpu_imx8q_set_system_cfg_common()
136 	config->cache_base_addr[0] = regs + MC_CACHE_0_BASE;  in vpu_imx8q_set_system_cfg_common()
139 	return 0;  in vpu_imx8q_set_system_cfg_common()
145 	csr_writel(core, IMX8Q_CSR_CM0Px_CPUWAIT, 0);  in vpu_imx8q_boot_core()
146 	return 0;  in vpu_imx8q_boot_core()
152 		return 0;  in vpu_imx8q_get_power_state()
165 	return 0;  in vpu_imx8q_on_firmware_loaded()
171 		{0x00000000, 0x08000000, VPU_CORE_MEMORY_CACHED},  in vpu_imx8q_check_memory_region()
172 		{0x08000000, 0x10000000, VPU_CORE_MEMORY_UNCACHED},  in vpu_imx8q_check_memory_region()
173 		{0x10000000, 0x20000000, VPU_CORE_MEMORY_CACHED},  in vpu_imx8q_check_memory_region()
174 		{0x20000000, 0x40000000, VPU_CORE_MEMORY_UNCACHED}  in vpu_imx8q_check_memory_region()
182 	for (i = 0; i < ARRAY_SIZE(imx8q_regions); i++) {  in vpu_imx8q_check_memory_region()
207 		return 0;  in vpu_imx8q_get_fuse()
219 		return 0;  in vpu_imx8q_get_fuse()