123 	reg_write(dev, reg, vc->dma_descs[pb].phys);  in tw686x_memcpy_dma_alloc()
168 		reg_write(vc->dev, reg, phys);  in tw686x_contig_buf_refill()
288 		reg_write(dev, reg, desc->phys);  in tw686x_sg_dma_alloc()
407 	reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], fps_map[i]);  in tw686x_set_framerate()
599 		reg_write(dev, BRIGHT[ch], ctrl->val & 0xff);  in tw686x_s_ctrl()
603 		reg_write(dev, CONTRAST[ch], ctrl->val);  in tw686x_s_ctrl()
607 		reg_write(dev, SAT_U[ch], ctrl->val);  in tw686x_s_ctrl()
608 		reg_write(dev, SAT_V[ch], ctrl->val);  in tw686x_s_ctrl()
612 		reg_write(dev, HUE[ch], ctrl->val & 0xff);  in tw686x_s_ctrl()
725 	reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);  in tw686x_set_format()
732 	reg_write(vc->dev, VDMA_WHP[vc->ch], val);  in tw686x_set_format()
791 	reg_write(vc->dev, SDT[vc->ch], val);  in tw686x_set_standard()
798 	reg_write(vc->dev, VIDEO_CONTROL1, val);  in tw686x_set_standard()
846 	reg_write(dev, SDT[vc->ch], 0x7);  in tw686x_querystd()
847 	reg_write(dev, SDT_EN[vc->ch], 0xff);  in tw686x_querystd()
857 	reg_write(dev, SDT[vc->ch], old_std);  in tw686x_querystd()
988 	reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);  in tw686x_set_input()
1214 		reg_write(dev, VDELAY_LO[ch], 0x14);  in tw686x_video_init()
1215 		reg_write(dev, HACTIVE_LO[ch], 0xd0);  in tw686x_video_init()
1216 		reg_write(dev, VIDEO_SIZE[ch], 0);  in tw686x_video_init()
1294 	reg_write(dev, PHASE_REF, val);  in tw686x_video_init()
1296 	reg_write(dev, MISC2[0], 0xe7);  in tw686x_video_init()
1297 	reg_write(dev, VCTRL1[0], 0xcc);  in tw686x_video_init()
1298 	reg_write(dev, LOOP[0], 0xa5);  in tw686x_video_init()
1300 		reg_write(dev, VCTRL1[1], 0xcc);  in tw686x_video_init()
1301 		reg_write(dev, LOOP[1], 0xa5);  in tw686x_video_init()
1302 		reg_write(dev, MISC2[1], 0xe7);  in tw686x_video_init()