pci/tw5864/tw5864-reg.h

17 /* DDR controller enabled */
30  * Video Frame mapping in DDR
76  * 0->3 4 VLC data buffer in DDR (1M each)
77  * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
147 /* DDR-DPR Burst Read Enable */
150  * DDR A/B Select as HOST access
156  * DDR Access Mode Select
157  * 0 Single R/W Access (Host <-> DDR)
287 /* DDR base address of OSD rectangle attribute data */
451  * Status of VLC stream in DDR (one bit for each buffer)
667  * 1 vlc stream to ddr buffers
699  * The system / DDR clock (166 MHz) is generated with an on-chip system clock
863  * Bit[1]: BURST DDR RAM interrupt
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1013 /* DDR Controller A */
1015  * [2:0] Data valid counter after read command to DDR. This is the delay value
1016  * to show how many cycles the data will be back from DDR after we issue a read
1056  * 0 256M DDR on board
1057  * 1 512M DDR on board
1058  * 2 1G DDR on board
1060  * 0 Only one DDR chip
1061  * 1 Two DDR chips
1068  * 1 DDR self-test mode
1072  * 0 DDR self-test single read/write
1073  * 1 DDR self-test burst read/write
1077  * 0 DDR self-test write command
1078  * 1 DDR self-test read command
1083  * 0 write 32'haaaa5555 to DDR
1084  * 1 write 32'hffffffff to DDR
1085  * 2 write 32'hha5a55a5a to DDR
1086  * 3 write increasing data to DDR
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1109  * DDR Controller B: same as 0xa000 ~ 0xa038, but add TW5864_DDR_B_OFFSET to all
1120 /* Audio data in to DDR enable (default 1) */
1122 /* Audio encode request to DDR enable (default 1) */
1124 /* Audio decode request0 to DDR enable (default 1) */
1126 /* Audio decode request1 to DDR enable (default 1) */
1128 /* VLC stream request to DDR enable (default 1) */
1130 /* H264 MV request to DDR enable (default 1) */
1132 /* mux_core MVD request to DDR enable (default 1) */
1134 /* mux_core MVD temp data request to DDR enable (default 1) */
1136 /* JPEG request to DDR enable (default 1) */
1138 /* mv_flag request to DDR enable (default 1) */
1230  * 1 MV is saved in DDR
1281 /* ddr burst enable (1 enable, and must set DDR_BRST_EN) */
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1415  * 0 Read Burst from DDR
1416  * 1 Write Burst to DDR
1419 /* Begin a new DDR Burst. This bit is self cleared */
1421 /* DDR Burst End Flag */
1423 /* Enable Error Interrupt for Single DDR Access */
1425 /* Enable Error Interrupt for Burst DDR Access */
1427 /* Enable Interrupt for End of DDR Burst Access */
1429 /* DDR Single Access Error Flag */
1431 /* DDR Single Access Busy Flag */
1433 /* DDR Burst Access Error Flag */
1435 /* DDR Burst Access Busy Flag */
1438 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1440 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
2061  * unit of 64K bytes. The generated DDR address will be {MD_BASE_ADDR,