pci/tw5864/tw5864-reg.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
49 #define TW5864_START_NSLICE BIT(15)
52  * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
57 /* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
63  * [15:10] H264 LPF_OFFSET Address
76  * 0->3 4 VLC data buffer in DDR (1M each)
77  * 0->7 8 VLC data buffer in DDR (512k each)
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
147 /* DDR-DPR Burst Read Enable */
157  * 0 Single R/W Access (Host <-> DDR)
158  * 1 Burst R/W Access (Host <-> DPR)
160 #define TW5864_DDR_MODE BIT(15)
163 /* SENIF_ORG_FRM_PTR [15:0] */
174  * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
181  * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR
185  * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR
190  * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
196  * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
203  * De-interlacer Mode
205  * 0 Normal Un-Shuffled Frame
210  * 11: Un-used
211  * 10: down-sample to 1/4
212  * 01: down-sample to 1/2
213  * 00: down-sample disabled
218  * 11: Un-used
219  * 10: down-sample to 1/4
220  * 01: down-sample to 1/2
221  * 00: down-sample disabled
270 /* [15:0] Lambda Value for H264 */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
371 /* [15:0] Horizontal Mirror for channel n */
373 /* [15:0] Vertical Mirror for channel n */
422  * Swap byte order of VLC stream in d-word.
424  * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]})
444 #define TW5864_VLC_PCI_SEL BIT(15)
477 /* [15:0] Total coefficient number in a frame */
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
517 /* ADPCM input data enable */
573  * Bit[17:15] ch5
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
606  * Bit[15:12] ch3
699  * The system / DDR clock (166 MHz) is generated with an on-chip system clock
700  * PLL (SYSPLL) using input crystal clock of 27 MHz. The system clock PLL
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
831  * Trigger mode of interrupt source 0 ~ 15
838 /* Enable of interrupt source 0 ~ 15 */
842 /* Clear interrupt command of interrupt source 0 ~ 15 */
847  * Assertion of interrupt source 0 ~ 15
848  * 1 High level or pos-edge is assertion
849  * 0 Low level or neg-edge is assertion
861  * Status of interrupt source 0 ~ 15
875  * Bit[13:15]: Reserved
891  * Bit[11:15]: Reserved
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
920  * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
926  * H264EN_CH_DNS[n] H264 Encoding Path Downscale Video Decoder Input for
974  * ..., [15:14]: H264EN_CH7_FMT
979  * ..., [15:14]: H264EN_CH15_FMT (?)
992  * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1050  * [15:0] Maximum average periodic refresh, the value is based on the current
1068  * 1 DDR self-test mode
1072  * 0 DDR self-test single read/write
1073  * 1 DDR self-test burst read/write
1077  * 0 DDR self-test write command
1078  * 1 DDR self-test read command
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1115 /* [15:0] Default is C013 */
1144 #define TW5864_ARB12_ENB BIT(15)
1145 /* ARB12 maximum value of time out counter (default 15"h1FF) */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1183  * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only)
1189  * [15:0] PCI Preview Path Enable for channel n
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1222 /* The configured status bit written into bit 15 of 0xfc04 */
1232 #define TW5864_MPI_DDR_SEL2 BIT(15)
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1312  * Every channel of preview and audio have ping-pong buffers in system memory,
1374  * Configuration register for 9[or 10] CIFs or 1D1+15QCIF Preview mode.
1376  * (1D1+15QCIF prev)
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1469  * 1 Sub-carrier PLL is locked to the incoming video source.
1470  * 0 Sub-carrier PLL is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505  * 0 = Non-standard signal
1506  * Read-only
1510  * 1 = Non-interlaced signal
1512  * Read-only
1559  * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1585  * output image. 1 through 15 provides sharpness enhancement with "F" being the
1598  * These bits control the brightness. They have value of -128 to 127 in 2's
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1641 /* Read-only */
1645  * Read-only.
1687  * process. This bit is a self-clearing bit
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1718  * Audio Input ADC gain control
1734  * 15 2.75
1746  * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1749  * 2 u-Law output
1750  * 3 A-Law output
1763  * audio input. It effects only for single chip or the last stage chip
1774  * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1781  * ACLKR input signal polarity inverse.
1787  * ACLKP input signal polarity inverse.
1820  * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1828  * ASYNR input signal delay.
1830  * 1 Add one 27MHz period delay in ASYNR signal input
1834  * ASYNP input signal delay.
1836  * 1 add one 27MHz period delay in ASYNP signal input
1840  * ADATP input data delay by one ACLKP clock.
1841  * 0 No delay (Default). This is for I2S type 1T delay input interface.
1842  * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1843  * type 0T delay input interface.
1847  * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1848  * 0 PCM input (Default)
1849  * 1 SB (Signed MSB bit in PCM data is inverted) input
1850  * 2 u-Law input
1851  * 3 A-Law input
1857  * for each input
1882  * Interrupt status register from the front-end. Write "1" to each bit to clear
1884  * 15:0 Motion detection interrupt for channel 0 ~ 15
1885  * 31:16 Night detection interrupt for channel 0 ~ 15
1886  * 47:32 Blind detection interrupt for channel 0 ~ 15
1887  * 63:48 No video interrupt for channel 0 ~ 15
1888  * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1889  * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1898  * 15:0 Motion detection interrupt for channel 0 ~ 15
1899  * 31:16 Night detection interrupt for channel 0 ~ 15
1900  * 47:32 Blind detection interrupt for channel 0 ~ 15
1901  * 63:48 No video interrupt for channel 0 ~ 15
1902  * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1903  * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1928 /* valid value for channel is [0:15] */
1963  * 15 Less Sensitive
1971  * 15 15 pixels
1996  * 15 Less sensitive
2003  * Define the threshold of sub-cell number for motion detection.
2004  * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005  * 1 Motion is detected if 2 sub-cells have motion
2006  * 2 Motion is detected if 3 sub-cells have motion
2007  * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2030  * 15 Less Sensitive
2038  * 15 High threshold (Less sensitive)
2047  * 15 High threshold (Less sensitive)
2072 /* [15:0] MD strobe has been performed at channel n (read only) */