intel/ipu6/ipu6.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2013 - 2024 Intel Corporation */
11 #include "ipu6-buttress.h"
17 #define IPU6_NAME			"intel-ipu6"
35  * IPU6 - TGL
36  * IPU6SE - JSL
37  * IPU6EP - ADL/RPL
38  * IPU6EP_MTL - MTL
96 /* The firmware is accessible within the first 2 GiB only in non-secure mode. */
116  * Threshold values are pre-defined and are arrived at after performance
123  * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on
147  * or Zero length write, is pre-fetch mechanism to pre-fetch the pages in
150  * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream
152  * L2 -> 16 streams and 32 blocks. 2 blocks per streams
154  * 2 blocks per L2 stream means, 1 stream points to 8MB range
165 /* Max L2 blocks per stream */
167 /* Max L1 blocks per stream */
180  * nr_l2streams = 0, means the MMU is of type MMU_V1 and do not support
183  * L1 stream per block sizes are configurable and varies per usecase.
184  * L2 has constant block sizes - 2 blocks per stream.
186  * MMU1 support pre-fetching of the pages to have less cache lookup misses. To
187  * enable the pre-fetching, MMU1 AT (Address Translator) device registers
191  * ZLW(Zero Length Write) is a mechanism to enable VT-d pre-fetching on IOMMU.
193  * 1. Sequential Access or 1D mode
194  *	Set ZLW_EN -> 1
195  *	set ZLW_PAGE_CROSS_1D -> 1
197  *		  N is pre-defined and hardcoded in the platform data
198  *	Set ZLW_2D -> 0
200  * 2. ZLW 2D mode
201  *	Set ZLW_EN -> 1
202  *	set ZLW_PAGE_CROSS_1D -> 1,
203  *	Set ZLW_N -> 0
204  *	Set ZLW_2D -> 1
206  * 3. ZLW Enable (no 1D or 2D mode)
207  *	Set ZLW_EN -> 1
208  *	set ZLW_PAGE_CROSS_1D -> 0,
209  *	Set ZLW_N -> 0
210  *	Set ZLW_2D -> 0
213  *	Set ZLW_EN -> 0
214  *	set ZLW_PAGE_CROSS_1D -> 0,
215  *	Set ZLW_N -> 0
216  *	Set ZLW_2D -> 0
220  * in the struct ipu6_mmu_hw. Each of these entries are per stream and
223  * a. l1_zlw_en -> To track zlw enabled per stream (ZLW_EN)
224  * b. l1_zlw_1d_mode -> Track 1D mode per stream. ZLW inserted at page boundary
225  * c. l1_ins_zlw_ahead_pages -> to track how advance the ZLW need to be inserted
227  * d. l1_zlw_2d_mode -> To track 2D mode per stream (ZLW_2D)
230  * Currently L1/L2 streams, blocks, AT ZLW configurations etc. are pre-defined
231  * as per the usecase specific calculations. Any change to this pre-defined
242 	 * L1 has variable blocks per stream - total of 64 blocks and maximum of
243 	 * 16 blocks per stream. Configurable by using the block start address
244 	 * per stream. Block start address is calculated from the block size
247 	/* Is ZLW is enabled in each stream */
258 	 * L2 has fixed 2 blocks per stream. Block address is calculated