Lines Matching full:l1
146 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW
148 * advance to the L1 and L2 caches without triggering any memory operations.
150 * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream
151 * One L1 block has 16 entries, hence points to 16 * 4K pages
153 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
163 /* One L2 entry maps 1024 L1 entries and one L1 entry per page */
167 /* Max L1 blocks per stream */
170 /* Entries per L1 block */
176 * In some of the IPU6 MMUs, there is provision to configure L1 and L2 page
177 * table caches. Both these L1 and L2 caches are divided into multiple sections
181 * L1/L2 page table caches.
183 * L1 stream per block sizes are configurable and varies per usecase.
221 * available only for the L1 streams.
230 * Currently L1/L2 streams, blocks, AT ZLW configurations etc. are pre-defined
242 * L1 has variable blocks per stream - total of 64 blocks and maximum of