Lines Matching +full:0 +full:x210000
11 * locates in one single space starts from 0 but in different sctions with
12 * different addresses, the subsystem offsets are defined to 0 as the
13 * register definition will have the address offset to 0.
15 #define IPU6_UNIFIED_OFFSET 0
17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000
18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500
19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00
21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000
22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700
23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00
24 #define IPU6_PSYS_IOMMUI_OFFSET 0x1b1500
27 #define IPU6_MMU_L1_STREAM_ID_REG_OFFSET 0x0c
28 #define IPU6_MMU_L2_STREAM_ID_REG_OFFSET 0x4c
29 #define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET 0x8c
31 #define IPU6_MMU_INFO_OFFSET 0x8
33 #define IPU6_ISYS_SPC_OFFSET 0x210000
35 #define IPU6SE_PSYS_SPC_OFFSET 0x110000
36 #define IPU6_PSYS_SPC_OFFSET 0x118000
38 #define IPU6_ISYS_DMEM_OFFSET 0x200000
39 #define IPU6_PSYS_DMEM_OFFSET 0x100000
41 #define IPU6_REG_ISYS_UNISPART_IRQ_EDGE 0x27c000
42 #define IPU6_REG_ISYS_UNISPART_IRQ_MASK 0x27c004
43 #define IPU6_REG_ISYS_UNISPART_IRQ_STATUS 0x27c008
44 #define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR 0x27c00c
45 #define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE 0x27c010
46 #define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE 0x27c014
47 #define IPU6_REG_ISYS_UNISPART_SW_IRQ_REG 0x27c414
48 #define IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG 0x27c418
53 #define IPU6_REG_ISYS_ISL_TOP_IRQ_EDGE 0x2b0200
54 #define IPU6_REG_ISYS_ISL_TOP_IRQ_MASK 0x2b0204
55 #define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS 0x2b0208
56 #define IPU6_REG_ISYS_ISL_TOP_IRQ_CLEAR 0x2b020c
57 #define IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE 0x2b0210
58 #define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE 0x2b0214
60 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE 0x2d2100
61 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK 0x2d2104
62 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_STATUS 0x2d2108
63 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_CLEAR 0x2d210c
64 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_ENABLE 0x2d2110
65 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_LEVEL_NOT_PULSE 0x2d2114
67 /* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */
68 #define IPU6_REG_ISYS_CDC_THRESHOLD(i) (0x27c400 + ((i) * 4))
77 #define IPU6_PKG_DIR_IMR_OFFSET 0x40
79 #define IPU6_ISYS_REG_SPC_STATUS_CTRL 0x0
87 #define IPU6_PSYS_REG_SPC_STATUS_CTRL 0x0
88 #define IPU6_PSYS_REG_SPC_START_PC 0x4
89 #define IPU6_PSYS_REG_SPC_ICACHE_BASE 0x10
90 #define IPU6_REG_PSYS_INFO_SEG_0_CONFIG_ICACHE_MASTER 0x14
98 #define IPU6_PSYS_REG_SPP0_STATUS_CTRL 0x20000
100 #define IPU6_INFO_ENABLE_SNOOP BIT(0)
116 * 0xE4 is from s2m MAS document. It means no remapping.
118 #define S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4
123 #define CSI_BE_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4
125 #define IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR 0x1ae000
126 #define IPU6_REG_DMA_TOP_AB_GROUP2_BASE_ADDR 0x1af000
127 #define IPU6_REG_DMA_TOP_AB_RING_MIN_OFFSET(n) (0x4 + (n) * 0xc)
128 #define IPU6_REG_DMA_TOP_AB_RING_MAX_OFFSET(n) (0x8 + (n) * 0xc)
129 #define IPU6_REG_DMA_TOP_AB_RING_ACCESS_OFFSET(n) (0xc + (n) * 0xc)
161 #define IPU6_REG_PSYS_GPDEV_IRQ_EDGE 0x1aa200
162 #define IPU6_REG_PSYS_GPDEV_IRQ_MASK 0x1aa204
163 #define IPU6_REG_PSYS_GPDEV_IRQ_STATUS 0x1aa208
164 #define IPU6_REG_PSYS_GPDEV_IRQ_CLEAR 0x1aa20c
165 #define IPU6_REG_PSYS_GPDEV_IRQ_ENABLE 0x1aa210
166 #define IPU6_REG_PSYS_GPDEV_IRQ_LEVEL_NOT_PULSE 0x1aa214
167 /* There are 8 FW interrupts, n = 0..7 */
177 #define IPU6_REG_PSYS_GPDEV_FWIRQ(n) (4 * (n) + 0x1aa100)