Lines Matching +full:slave +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
13 #include "ipu6-bus.h"
14 #include "ipu6-isys.h"
15 #include "ipu6-platform-isys-csi2-reg.h"
31 * - req: 0 for read, 1 for write
32 * - 12 bits address
33 * - 8bits data (will ignore for read)
34 * --24----16------4-----0
35 * --|-data-|-addr-|-req-|
37 #define IFC_REQ(req, addr, data) (FIELD_PREP(GENMASK(23, 16), data) | \ argument
38 FIELD_PREP(GENMASK(15, 4), addr) | \
63 static void dwc_dphy_write(struct ipu6_isys *isys, u32 phy_id, u32 addr, in dwc_dphy_write() argument
66 struct device *dev = &isys->adev->auxdev.dev; in dwc_dphy_write()
67 void __iomem *isys_base = isys->pdata->base; in dwc_dphy_write()
70 dev_dbg(dev, "write: reg 0x%lx = data 0x%x", base + addr - isys_base, in dwc_dphy_write()
72 writel(data, base + addr); in dwc_dphy_write()
75 static u32 dwc_dphy_read(struct ipu6_isys *isys, u32 phy_id, u32 addr) in dwc_dphy_read() argument
77 struct device *dev = &isys->adev->auxdev.dev; in dwc_dphy_read()
78 void __iomem *isys_base = isys->pdata->base; in dwc_dphy_read()
82 data = readl(base + addr); in dwc_dphy_read()
83 dev_dbg(dev, "read: reg 0x%lx = data 0x%x", base + addr - isys_base, in dwc_dphy_read()
89 static void dwc_dphy_write_mask(struct ipu6_isys *isys, u32 phy_id, u32 addr, in dwc_dphy_write_mask() argument
95 mask = (1 << width) - 1; in dwc_dphy_write_mask()
96 temp = dwc_dphy_read(isys, phy_id, addr); in dwc_dphy_write_mask()
99 dwc_dphy_write(isys, phy_id, addr, temp); in dwc_dphy_write_mask()
103 u32 addr, u8 shift, u8 width) in dwc_dphy_read_mask() argument
107 val = dwc_dphy_read(isys, phy_id, addr) >> shift; in dwc_dphy_read_mask()
108 return val & ((1 << width) - 1); in dwc_dphy_read_mask()
112 static int dwc_dphy_ifc_read(struct ipu6_isys *isys, u32 phy_id, u32 addr, in dwc_dphy_ifc_read() argument
115 struct device *dev = &isys->adev->auxdev.dev; in dwc_dphy_ifc_read()
116 void __iomem *isys_base = isys->pdata->base; in dwc_dphy_ifc_read()
123 IFC_REQ(TEST_IFC_REQ_READ, addr, 0)); in dwc_dphy_ifc_read()
134 dev_dbg(dev, "DWC ifc read 0x%x = 0x%x", addr, *val); in dwc_dphy_ifc_read()
139 static int dwc_dphy_ifc_write(struct ipu6_isys *isys, u32 phy_id, u32 addr, in dwc_dphy_ifc_write() argument
142 struct device *dev = &isys->adev->auxdev.dev; in dwc_dphy_ifc_write()
143 void __iomem *isys_base = isys->pdata->base; in dwc_dphy_ifc_write()
150 IFC_REQ(TEST_IFC_REQ_WRITE, addr, data)); in dwc_dphy_ifc_write()
162 u32 addr, u32 data, u8 shift, u8 width) in dwc_dphy_ifc_write_mask() argument
167 ret = dwc_dphy_ifc_read(isys, phy_id, addr, &temp); in dwc_dphy_ifc_write_mask()
171 mask = (1 << width) - 1; in dwc_dphy_ifc_write_mask()
174 dwc_dphy_ifc_write(isys, phy_id, addr, temp); in dwc_dphy_ifc_write_mask()
177 static u32 dwc_dphy_ifc_read_mask(struct ipu6_isys *isys, u32 phy_id, u32 addr, in dwc_dphy_ifc_read_mask() argument
183 ret = dwc_dphy_ifc_read(isys, phy_id, addr, &val); in dwc_dphy_ifc_read_mask()
187 return ((val >> shift) & ((1 << width) - 1)); in dwc_dphy_ifc_read_mask()
192 struct device *dev = &isys->adev->auxdev.dev; in dwc_dphy_pwr_up()
293 while (i--) { in get_hsfreq_by_mbps()
305 struct ipu6_bus_device *adev = isys->adev; in ipu6_isys_dwc_phy_config()
306 struct device *dev = &adev->auxdev.dev; in ipu6_isys_dwc_phy_config()
307 struct ipu6_device *isp = adev->isp; in ipu6_isys_dwc_phy_config()
317 return -EINVAL; in ipu6_isys_dwc_phy_config()
324 if (isys->phy_termcal_val) { in ipu6_isys_dwc_phy_config()
328 isys->phy_termcal_val, 4, 4); in ipu6_isys_dwc_phy_config()
353 * Set cfgclkfreqrange[5:0] = round[(Fcfg_clk(MHz)-17)*4] in ipu6_isys_dwc_phy_config()
354 * (38.4 - 17) * 4 = ~85 (0x55) in ipu6_isys_dwc_phy_config()
356 cfg_clk_freqrange = (isp->buttress.ref_clk - 170) * 4 / 10; in ipu6_isys_dwc_phy_config()
358 isp->buttress.ref_clk, cfg_clk_freqrange); in ipu6_isys_dwc_phy_config()
369 u32 slave, u32 mbps) in ipu6_isys_dwc_phy_aggr_setup() argument
373 dwc_dphy_ifc_write_mask(isys, slave, 0x133, 0x0, 0, 1); in ipu6_isys_dwc_phy_aggr_setup()
377 dwc_dphy_ifc_write_mask(isys, slave, 0x307, 0x0, 2, 1); in ipu6_isys_dwc_phy_aggr_setup()
381 dwc_dphy_ifc_write_mask(isys, slave, 0x508, 0x1, 5, 1); in ipu6_isys_dwc_phy_aggr_setup()
383 dwc_dphy_ifc_write_mask(isys, slave, 0x708, 0x1, 5, 1); in ipu6_isys_dwc_phy_aggr_setup()
385 /* Config slave PHY clk lane to bypass long channel clk to DDR clk */ in ipu6_isys_dwc_phy_aggr_setup()
387 dwc_dphy_ifc_write_mask(isys, slave, 0x308, 0x1, 3, 1); in ipu6_isys_dwc_phy_aggr_setup()
389 /* Override slave PHY clk lane enable (DPHYRXCLK_CLL_demux module) */ in ipu6_isys_dwc_phy_aggr_setup()
390 dwc_dphy_ifc_write_mask(isys, slave, 0xe0, 0x3, 0, 2); in ipu6_isys_dwc_phy_aggr_setup()
392 /* Override slave PHY DDR clk lane enable (DPHYHSRX_div124 module) */ in ipu6_isys_dwc_phy_aggr_setup()
393 dwc_dphy_ifc_write_mask(isys, slave, 0xe1, 0x1, 1, 1); in ipu6_isys_dwc_phy_aggr_setup()
394 dwc_dphy_ifc_write_mask(isys, slave, 0x307, 0x1, 3, 1); in ipu6_isys_dwc_phy_aggr_setup()
396 /* Turn off slave PHY LP-RX clk lane */ in ipu6_isys_dwc_phy_aggr_setup()
397 dwc_dphy_ifc_write_mask(isys, slave, 0x304, 0x1, 7, 1); in ipu6_isys_dwc_phy_aggr_setup()
398 dwc_dphy_ifc_write_mask(isys, slave, 0x305, 0xa, 0, 5); in ipu6_isys_dwc_phy_aggr_setup()
404 struct device *dev = &isys->adev->auxdev.dev; in ipu6_isys_dwc_phy_powerup_ack()
420 if (phy_id != PHY_E || isys->phy_termcal_val) in ipu6_isys_dwc_phy_powerup_ack()
426 isys->phy_termcal_val = dwc_dphy_ifc_read_mask(isys, phy_id, in ipu6_isys_dwc_phy_powerup_ack()
429 isys->phy_termcal_val); in ipu6_isys_dwc_phy_powerup_ack()
437 dev_dbg(&isys->adev->auxdev.dev, "Reset phy %u", phy_id); in ipu6_isys_dwc_phy_reset()
452 struct device *dev = &isys->adev->auxdev.dev; in ipu6_isys_dwc_phy_set_power()
453 void __iomem *isys_base = isys->pdata->base; in ipu6_isys_dwc_phy_set_power()
459 port = cfg->port; in ipu6_isys_dwc_phy_set_power()
461 if (!isys_base || port >= isys->pdata->ipdata->csi2.nports) { in ipu6_isys_dwc_phy_set_power()
463 return -EINVAL; in ipu6_isys_dwc_phy_set_power()
466 nlanes = cfg->nlanes; in ipu6_isys_dwc_phy_set_power()
469 dev_err(dev, "invalid csi-port %u with %u lanes\n", port, in ipu6_isys_dwc_phy_set_power()
471 return -EINVAL; in ipu6_isys_dwc_phy_set_power()
474 link_freq = ipu6_isys_csi2_get_link_freq(&isys->csi2[port]); in ipu6_isys_dwc_phy_set_power()
510 dev_dbg(dev, "config phy %u with %u lanes in non-aggr mode\n", in ipu6_isys_dwc_phy_set_power()