54 	PHY_FSM_STATE_OFFSETCAL = 5,
111 #define DWC_DPHY_TIMEOUT (5 * USEC_PER_SEC)
289 static u16 get_hsfreq_by_mbps(u32 mbps)  in get_hsfreq_by_mbps()  argument
294 		if (freqranges[i].default_mbps == mbps ||  in get_hsfreq_by_mbps()
295 		    (mbps >= freqranges[i].min && mbps <= freqranges[i].max))  in get_hsfreq_by_mbps()
303 				    u32 phy_id, u32 mbps)  in ipu6_isys_dwc_phy_config()  argument
312 	dev_dbg(dev, "config Dphy %u with %u mbps", phy_id, mbps);  in ipu6_isys_dwc_phy_config()
314 	index = get_hsfreq_by_mbps(mbps);  in ipu6_isys_dwc_phy_config()
316 		dev_err(dev, "link freq not found for mbps %u", mbps);  in ipu6_isys_dwc_phy_config()
347 	if (mbps < 1500) {  in ipu6_isys_dwc_phy_config()
349 		dwc_dphy_ifc_write_mask(isys, phy_id, 0x8, 0x1, 5, 1);  in ipu6_isys_dwc_phy_config()
353 	 * Set cfgclkfreqrange[5:0] = round[(Fcfg_clk(MHz)-17)*4]  in ipu6_isys_dwc_phy_config()
369 					 u32 slave, u32 mbps)  in ipu6_isys_dwc_phy_aggr_setup()  argument
380 	dwc_dphy_ifc_write_mask(isys, master, 0x508, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
381 	dwc_dphy_ifc_write_mask(isys, slave, 0x508, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
382 	dwc_dphy_ifc_write_mask(isys, master, 0x708, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
383 	dwc_dphy_ifc_write_mask(isys, slave, 0x708, 0x1, 5, 1);  in ipu6_isys_dwc_phy_aggr_setup()
398 	dwc_dphy_ifc_write_mask(isys, slave, 0x305, 0xa, 0, 5);  in ipu6_isys_dwc_phy_aggr_setup()
455 	u32 nlanes, port, mbps;  in ipu6_isys_dwc_phy_set_power()  local
480 	mbps = div_u64(link_freq, 500000);  in ipu6_isys_dwc_phy_set_power()
493 						     secondary, mbps);  in ipu6_isys_dwc_phy_set_power()
495 			ret = ipu6_isys_dwc_phy_config(isys, primary, mbps);  in ipu6_isys_dwc_phy_set_power()
498 			ret = ipu6_isys_dwc_phy_config(isys, secondary, mbps);  in ipu6_isys_dwc_phy_set_power()
514 		ret = ipu6_isys_dwc_phy_config(isys, phy_id, mbps);  in ipu6_isys_dwc_phy_set_power()