41 #define DM1105_BOARD_UNKNOWN			0
52 #define PCI_VENDOR_ID_TRIGEM	0x109f
55 #define PCI_VENDOR_ID_AXESS	0x195d
58 #define PCI_DEVICE_ID_DM1105	0x036f
61 #define PCI_DEVICE_ID_DW2002	0x2002
64 #define PCI_DEVICE_ID_DW2004	0x2004
67 #define PCI_DEVICE_ID_DM05	0x1105
73 #define DM1105_TSCTR				0x00
74 #define DM1105_DTALENTH				0x04
77 #define DM1105_GPIOVAL				0x08
78 #define DM1105_GPIOCTR				0x0c
81 #define DM1105_PIDN				0x10
84 #define DM1105_CWSEL				0x14
87 #define DM1105_HOST_CTR				0x18
88 #define DM1105_HOST_AD				0x1c
91 #define DM1105_CR				0x30
92 #define DM1105_RST				0x34
93 #define DM1105_STADR				0x38
94 #define DM1105_RLEN				0x3c
95 #define DM1105_WRP				0x40
96 #define DM1105_INTCNT				0x44
97 #define DM1105_INTMAK				0x48
98 #define DM1105_INTSTS				0x4c
101 #define DM1105_ODD				0x50
102 #define DM1105_EVEN				0x58
105 #define DM1105_PID				0x60
108 #define DM1105_IRCTR				0x64
109 #define DM1105_IRMODE				0x68
110 #define DM1105_SYSTEMCODE			0x6c
111 #define DM1105_IRCODE				0x70
114 #define DM1105_ENCRYPT				0x74
115 #define DM1105_VER				0x7c
118 #define DM1105_I2CCTR				0x80
119 #define DM1105_I2CSTS				0x81
120 #define DM1105_I2CDAT				0x82
121 #define DM1105_I2C_RA				0x83
125 #define INTMAK_TSIRQM				0x01
126 #define INTMAK_HIRQM				0x04
127 #define INTMAK_IRM				0x08
131 #define INTMAK_NONEMASK				0x00
134 #define INTSTS_TSIRQ				0x01
135 #define INTSTS_HIRQ				0x04
136 #define INTSTS_IR				0x08
139 #define DM1105_IR_EN				0x01
140 #define DM1105_SYS_CHK				0x02
141 #define DM1105_REP_FLG				0x08
144 #define IIC_24C01_addr				0xa0
146 #define DM1105_MAX				0x04
162 #define GPIO_ALL				0x03ffff
178 #define UNBR_LNB_OFF				0
182 static unsigned int card[]  = {[0 ... 3] = UNSET };
260 		.subvendor = 0x0000,
261 		.subdevice = 0x2002,
264 		.subvendor = 0x0001,
265 		.subdevice = 0x2002,
268 		.subvendor = 0x0000,
269 		.subdevice = 0x2004,
272 		.subvendor = 0x0001,
273 		.subdevice = 0x2004,
276 		.subvendor = 0x195d,
277 		.subdevice = 0x1105,
286 	if (0 == pci->subsystem_vendor &&  in dm1105_card_list()
287 			0 == pci->subsystem_device) {  in dm1105_card_list()
304 	for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)  in dm1105_card_list()
374 #define dm_clearl(reg, bit)	dm_andorl((reg), (bit), 0)
382 	if (mask & 0xfffc0000)  in dm1105_gpio_set()
385 	if (mask & 0x0003ffff)  in dm1105_gpio_set()
386 		dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);  in dm1105_gpio_set()
392 	if (mask & 0xfffc0000)  in dm1105_gpio_clear()
395 	if (mask & 0x0003ffff)  in dm1105_gpio_clear()
396 		dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);  in dm1105_gpio_clear()
402 	if (mask & 0xfffc0000)  in dm1105_gpio_andor()
405 	if (mask & 0x0003ffff)  in dm1105_gpio_andor()
406 		dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);  in dm1105_gpio_andor()
412 	if (mask & 0xfffc0000)  in dm1105_gpio_get()
415 	if (mask & 0x0003ffff)  in dm1105_gpio_get()
416 		return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;  in dm1105_gpio_get()
418 	return 0;  in dm1105_gpio_get()
423 	if (mask & 0xfffc0000)  in dm1105_gpio_enable()
426 	if ((mask & 0x0003ffff) && asoutput)  in dm1105_gpio_enable()
427 		dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);  in dm1105_gpio_enable()
428 	else if ((mask & 0x0003ffff) && !asoutput)  in dm1105_gpio_enable()
429 		dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);  in dm1105_gpio_enable()
436 		dm1105_gpio_enable(dev, line, 0);  in dm1105_setline()
462 									? 1 : 0;  in dm1105_getsda()
470 									? 1 : 0;  in dm1105_getscl()
482 	for (i = 0; i < num; i++) {  in dm1105_i2c_xfer()
483 		dm_writeb(DM1105_I2CCTR, 0x00);  in dm1105_i2c_xfer()
489 			for (byte = 0; byte < msgs[i].len; byte++)  in dm1105_i2c_xfer()
490 				dm_writeb(DM1105_I2CDAT + byte + 1, 0);  in dm1105_i2c_xfer()
492 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
493 			for (j = 0; j < 55; j++) {  in dm1105_i2c_xfer()
496 				if ((status & 0xc0) == 0x40)  in dm1105_i2c_xfer()
502 			for (byte = 0; byte < msgs[i].len; byte++) {  in dm1105_i2c_xfer()
504 				if (rc < 0)  in dm1105_i2c_xfer()
508 		} else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {  in dm1105_i2c_xfer()
515 				dm_writeb(DM1105_I2CDAT + 1, 0xf7);  in dm1105_i2c_xfer()
516 				for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {  in dm1105_i2c_xfer()
520 				dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));  in dm1105_i2c_xfer()
521 				for (j = 0; j < 25; j++) {  in dm1105_i2c_xfer()
524 					if ((status & 0xc0) == 0x40)  in dm1105_i2c_xfer()
533 			} while (len > 0);  in dm1105_i2c_xfer()
537 			for (byte = 0; byte < msgs[i].len; byte++) {  in dm1105_i2c_xfer()
541 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
542 			for (j = 0; j < 25; j++) {  in dm1105_i2c_xfer()
545 				if ((status & 0xc0) == 0x40)  in dm1105_i2c_xfer()
597 	return 0;  in dm1105_set_voltage()
629 	dm_writeb(DM1105_CR, 0);  in dm1105_disable_irqs()
636 	if (dev->full_ts_users++ == 0)  in dm1105_start_feed()
639 	return 0;  in dm1105_start_feed()
646 	if (--dev->full_ts_users == 0)  in dm1105_stop_feed()
649 	return 0;  in dm1105_stop_feed()
660 		printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);  in dm1105_emit_key()
662 	data = (ircom >> 8) & 0x7f;  in dm1105_emit_key()
665 	rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0);  in dm1105_emit_key()
676 	if (!((dev->ts_buf[oldwrp] == 0x47) &&  in dm1105_dmx_buffer()
677 			(dev->ts_buf[oldwrp + 188] == 0x47) &&  in dm1105_dmx_buffer()
678 			(dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {  in dm1105_dmx_buffer()
682 				(dev->dmarst == 0)) {  in dm1105_dmx_buffer()
684 			dev->wrp = 0;  in dm1105_dmx_buffer()
685 			dev->PacketErrorCount = 0;  in dm1105_dmx_buffer()
686 			dev->dmarst = 0;  in dm1105_dmx_buffer()
754 	if (err < 0) {  in dm1105_ir_init()
760 	return 0;  in dm1105_ir_init()
772 	dm_writeb(DM1105_HOST_CTR, 0);  in dm1105_hw_init()
777 	dm_writew(DM1105_TSCTR, 0xc10a);  in dm1105_hw_init()
788 	dm_writeb(DM1105_IRMODE, 0);  in dm1105_hw_init()
789 	dm_writew(DM1105_SYSTEMCODE, 0);  in dm1105_hw_init()
791 	return 0;  in dm1105_hw_init()
799 	dm_writeb(DM1105_IRCTR, 0);  in dm1105_hw_exit()
806 	.demod_address = 0x68,
810 	.skip_reinit = 0,
818 	.demod_address = 0x68,
823 	.demod_address = 0x68,
829 	.demod_address = 0x55,
833 	.demod_address = 0x68,
837 	.tuner_address = 0x60,
857 			dvb_attach(dvb_pll_attach, dev->fe, 0x60,  in frontend_init()
867 			dvb_attach(stb6000_attach, dev->fe, 0x61,  in frontend_init()
905 			dvb_attach(dvb_pll_attach, dev->fe, 0x60,  in frontend_init()
915 			dvb_attach(stb6000_attach, dev->fe, 0x61,  in frontend_init()
934 	if (ret < 0) {  in frontend_init()
941 	return 0;  in frontend_init()
946 	static u8 command[1] = { 0x28 };  in dm1105_read_mac()
951 			.flags = 0,  in dm1105_read_mac()
988 	for (i = 0; UNSET == dev->boardnr &&  in dm1105_probe()
1004 	dev->PacketErrorCount = 0;  in dm1105_probe()
1005 	dev->dmarst = 0;  in dm1105_probe()
1008 	if (ret < 0)  in dm1105_probe()
1012 	if (ret < 0)  in dm1105_probe()
1018 	if (ret < 0)  in dm1105_probe()
1021 	dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));  in dm1105_probe()
1031 	if (ret < 0)  in dm1105_probe()
1043 	if (ret < 0)  in dm1105_probe()
1065 	if (ret < 0)  in dm1105_probe()
1071 	if (ret < 0)  in dm1105_probe()
1086 	if (ret < 0)  in dm1105_probe()
1092 	dev->dmxdev.capabilities = 0;  in dm1105_probe()
1095 	if (ret < 0)  in dm1105_probe()
1101 	if (ret < 0)  in dm1105_probe()
1107 	if (ret < 0)  in dm1105_probe()
1111 	if (ret < 0)  in dm1105_probe()
1115 	if (ret < 0)  in dm1105_probe()
1119 	if (ret < 0)  in dm1105_probe()
1134 	if (ret < 0)  in dm1105_probe()
1137 	return 0;  in dm1105_probe()