23 #define CX23888_IR_REG_BASE	0x170000
26  * to the CX23885 register offsets of 0x200 through 0x218
28 #define CX23888_IR_CNTRL_REG	0x170000
29 #define CNTRL_WIN_3_3	0x00000000
30 #define CNTRL_WIN_4_3	0x00000001
31 #define CNTRL_WIN_3_4	0x00000002
32 #define CNTRL_WIN_4_4	0x00000003
33 #define CNTRL_WIN	0x00000003
34 #define CNTRL_EDG_NONE	0x00000000
35 #define CNTRL_EDG_FALL	0x00000004
36 #define CNTRL_EDG_RISE	0x00000008
37 #define CNTRL_EDG_BOTH	0x0000000C
38 #define CNTRL_EDG	0x0000000C
39 #define CNTRL_DMD	0x00000010
40 #define CNTRL_MOD	0x00000020
41 #define CNTRL_RFE	0x00000040
42 #define CNTRL_TFE	0x00000080
43 #define CNTRL_RXE	0x00000100
44 #define CNTRL_TXE	0x00000200
45 #define CNTRL_RIC	0x00000400
46 #define CNTRL_TIC	0x00000800
47 #define CNTRL_CPL	0x00001000
48 #define CNTRL_LBM	0x00002000
49 #define CNTRL_R		0x00004000
51 #define CNTRL_IVO	0x00008000
53 #define CX23888_IR_TXCLK_REG	0x170004
54 #define TXCLK_TCD	0x0000FFFF
56 #define CX23888_IR_RXCLK_REG	0x170008
57 #define RXCLK_RCD	0x0000FFFF
59 #define CX23888_IR_CDUTY_REG	0x17000C
60 #define CDUTY_CDC	0x0000000F
62 #define CX23888_IR_STATS_REG	0x170010
63 #define STATS_RTO	0x00000001
64 #define STATS_ROR	0x00000002
65 #define STATS_RBY	0x00000004
66 #define STATS_TBY	0x00000008
67 #define STATS_RSR	0x00000010
68 #define STATS_TSR	0x00000020
70 #define CX23888_IR_IRQEN_REG	0x170014
71 #define IRQEN_RTE	0x00000001
72 #define IRQEN_ROE	0x00000002
73 #define IRQEN_RSE	0x00000010
74 #define IRQEN_TSE	0x00000020
76 #define CX23888_IR_FILTR_REG	0x170018
77 #define FILTR_LPF	0x0000FFFF
79 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
80 #define CX23888_IR_FIFO_REG	0x170040
81 #define FIFO_RXTX	0x0000FFFF
82 #define FIFO_RXTX_LVL	0x00010000
83 #define FIFO_RXTX_RTO	0x0001FFFF
84 #define FIFO_RX_NDV	0x00020000
89 #define CX23888_IR_SEEDP_REG	0x17001C
90 #define CX23888_IR_TIMOL_REG	0x170020
91 #define CX23888_IR_WAKE0_REG	0x170024
92 #define CX23888_IR_WAKE1_REG	0x170028
93 #define CX23888_IR_WAKE2_REG	0x17002C
94 #define CX23888_IR_MASK0_REG	0x170030
95 #define CX23888_IR_MASK1_REG	0x170034
96 #define CX23888_IR_MAKS2_REG	0x170038
97 #define CX23888_IR_DPIPG_REG	0x17003C
98 #define CX23888_IR_LEARN_REG	0x170044
145 	return 0;  in cx23888_ir_write4()
157 	return 0;  in cx23888_ir_and_or4()
163  * Note the largest clock divider value of 0xffff corresponds to:
164  *	(0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
199  * Note the largest count value of 0xffff corresponds to:
200  *	0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
208 		d = 0;  in count_to_lpf_count()
252 	 * the (count << 2) | 0x3  in pulse_width_count_to_ns()
254 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */  in pulse_width_count_to_ns()
268 	 * the (count << 2) | 0x3  in pulse_width_count_to_us()
270 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */  in pulse_width_count_to_us()
282  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
298 	do_div(count, (FIFO_RXTX << 2) | 0x3);  in pulse_clocks_to_clock_divider()
314 	TX_FIFO_HALF_EMPTY = 0,
319 	RX_FIFO_HALF_FULL = 0,
338 			   enable ? (CNTRL_TXE | CNTRL_TFE) : 0);  in control_tx_enable()
344 			   enable ? (CNTRL_RXE | CNTRL_RFE) : 0);  in control_rx_enable()
351 			   enable ? CNTRL_MOD : 0);  in control_tx_modulation_enable()
358 			   enable ? CNTRL_DMD : 0);  in control_rx_demodulation_enable()
398 			   invert ? CNTRL_CPL : 0);  in control_tx_polarity_invert()
405 			   invert ? CNTRL_IVO : 0);  in control_tx_level_invert()
463 	if (n != 0)  in cduty_tx_s_duty_cycle()
552 		irqenable_tx(dev, 0);  in cx23888_ir_irq_handler()
561 	kror = 0;  in cx23888_ir_irq_handler()
568 		for (i = 0, v = FIFO_RX_NDV;  in cx23888_ir_irq_handler()
569 		     (v & FIFO_RX_NDV) && !kror; i = 0) {  in cx23888_ir_irq_handler()
570 			for (j = 0;  in cx23888_ir_irq_handler()
576 			if (i == 0)  in cx23888_ir_irq_handler()
588 	events = 0;  in cx23888_ir_irq_handler()
589 	v = 0;  in cx23888_ir_irq_handler()
625 	return 0;  in cx23888_ir_irq_handler()
642 	if (n == 0) {  in cx23888_ir_rx_read()
643 		*num = 0;  in cx23888_ir_rx_read()
644 		return 0;  in cx23888_ir_rx_read()
652 	for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {  in cx23888_ir_rx_read()
656 			u = 0;  in cx23888_ir_rx_read()
659 			u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;  in cx23888_ir_rx_read()
661 				u = u ? 0 : 1;  in cx23888_ir_rx_read()
662 			w = 0;  in cx23888_ir_rx_read()
678 	return 0;  in cx23888_ir_rx_read()
688 	return 0;  in cx23888_ir_rx_g_parameters()
699 	irqenable_rx(dev, 0);  in cx23888_ir_rx_shutdown()
703 	filter_rx_s_min_width(dev, 0);  in cx23888_ir_rx_shutdown()
709 	return 0;  in cx23888_ir_rx_shutdown()
736 	irqenable_rx(dev, 0);  in cx23888_ir_rx_s_parameters()
796 	return 0;  in cx23888_ir_rx_s_parameters()
808 	return 0;  in cx23888_ir_tx_write()
818 	return 0;  in cx23888_ir_tx_g_parameters()
829 	irqenable_tx(dev, 0);  in cx23888_ir_tx_shutdown()
837 	return 0;  in cx23888_ir_tx_shutdown()
864 	irqenable_tx(dev, 0);  in cx23888_ir_tx_s_parameters()
909 	return 0;  in cx23888_ir_tx_s_parameters()
983 			i = 0;  in cx23888_ir_log_status()
984 			j = 0;  in cx23888_ir_log_status()
1046 	return 0;  in cx23888_ir_log_status()
1056 	if ((addr & 0x3) != 0)  in cx23888_ir_g_register()
1062 	return 0;  in cx23888_ir_g_register()
1071 	if ((addr & 0x3) != 0)  in cx23888_ir_s_register()
1076 	return 0;  in cx23888_ir_s_register()
1166 	if (ret == 0) {  in cx23888_ir_probe()
1172 		cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);  in cx23888_ir_probe()
1204 	return 0;  in cx23888_ir_remove()