Lines Matching +full:0 +full:x040000
13 #define MGR_CMD_MASK 0x40000000
16 #define MGR_CMD_MASK_ACK (MGR_CMD_MASK | 0x80000000)
19 IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
21 OUT[0] - Task handle. This handle is passed along with commands to
24 #define CX18_CREATE_TASK (MGR_CMD_MASK | 0x0001)
27 IN[0] - Task handle. Hanlde of the task to destroy
29 #define CX18_DESTROY_TASK (MGR_CMD_MASK | 0x0002)
32 #define CPU_CMD_MASK 0x20000000
33 #define CPU_CMD_MASK_DEBUG (CPU_CMD_MASK | 0x00000000)
34 #define CPU_CMD_MASK_ACK (CPU_CMD_MASK | 0x80000000)
35 #define CPU_CMD_MASK_CAPTURE (CPU_CMD_MASK | 0x00020000)
36 #define CPU_CMD_MASK_TS (CPU_CMD_MASK | 0x00040000)
38 #define EPU_CMD_MASK 0x02000000
39 #define EPU_CMD_MASK_DEBUG (EPU_CMD_MASK | 0x000000)
40 #define EPU_CMD_MASK_DE (EPU_CMD_MASK | 0x040000)
42 #define APU_CMD_MASK 0x10000000
43 #define APU_CMD_MASK_ACK (APU_CMD_MASK | 0x80000000)
45 #define CX18_APU_ENCODING_METHOD_MPEG (0 << 28)
49 IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
50 IN[1] - caller buffer address, or 0
52 #define CX18_APU_START (APU_CMD_MASK | 0x01)
55 IN[0] - encoding method to stop
57 #define CX18_APU_STOP (APU_CMD_MASK | 0x02)
61 #define CX18_APU_RESETAI (APU_CMD_MASK | 0x05)
65 IN[0] - Task handle. Handle of the task
69 #define CX18_EPU_DMA_DONE (EPU_CMD_MASK_DE | 0x0001)
72 IN[0] - A value to log
74 0/zero/NULL means "I have nothing to say" */
75 #define CX18_EPU_DEBUG (EPU_CMD_MASK_DEBUG | 0x0003)
78 IN[0] - Address
80 #define CX18_CPU_DEBUG_PEEK32 (CPU_CMD_MASK_DEBUG | 0x0003)
83 IN[0] - Task handle. Handle of the task to start
85 #define CX18_CPU_CAPTURE_START (CPU_CMD_MASK_CAPTURE | 0x0002)
88 IN[0] - Task handle. Handle of the task to stop
89 IN[1] - 0 = stop at end of GOP, 1 = stop at end of frame (MPEG only)
91 #define CX18_CPU_CAPTURE_STOP (CPU_CMD_MASK_CAPTURE | 0x0003)
94 IN[0] - Task handle. Handle of the task to pause
96 #define CX18_CPU_CAPTURE_PAUSE (CPU_CMD_MASK_CAPTURE | 0x0007)
99 IN[0] - Task handle. Handle of the task to resume
101 #define CX18_CPU_CAPTURE_RESUME (CPU_CMD_MASK_CAPTURE | 0x0008)
103 #define CAPTURE_CHANNEL_TYPE_NONE 0
115 IN[0] - Task handle. Handle of the task to start
121 IN[0] - task handle. Handle of the task to start
124 #define CX18_CPU_SET_STREAM_OUTPUT_TYPE (CPU_CMD_MASK_CAPTURE | 0x0012)
127 IN[0] - task handle
132 IN[5] - frame rate, 0 - 29.97f/s, 1 - 25f/s
134 #define CX18_CPU_SET_VIDEO_IN (CPU_CMD_MASK_CAPTURE | 0x0004)
137 IN[0] - task handle. Handle of the task to start
143 #define CX18_CPU_SET_VIDEO_RATE (CPU_CMD_MASK_CAPTURE | 0x0005)
146 IN[0] - task handle
150 #define CX18_CPU_SET_VIDEO_RESOLUTION (CPU_CMD_MASK_CAPTURE | 0x0006)
153 IN[0] - Task handle. Handle of the task
154 IN[1] - type, 0 - temporal, 1 - spatial, 2 - median
155 IN[2] - mode, temporal/spatial: 0 - disable, 1 - static, 2 - dynamic
156 median: 0 = disable, 1 = horizontal, 2 = vertical,
158 IN[3] - strength, temporal 0 - 31, spatial 0 - 15
160 #define CX18_CPU_SET_FILTER_PARAM (CPU_CMD_MASK_CAPTURE | 0x0009)
163 IN[0] - Task handle.
164 IN[1] - luma type: 0 = disable, 1 = 1D horizontal only, 2 = 1D vertical only,
166 IN[2] - chroma type: 0 - disable, 1 = 1D horizontal
168 #define CX18_CPU_SET_SPATIAL_FILTER_TYPE (CPU_CMD_MASK_CAPTURE | 0x000C)
171 IN[0] - Task handle.
177 #define CX18_CPU_SET_MEDIAN_CORING (CPU_CMD_MASK_CAPTURE | 0x000E)
180 IN[0] - Task handle (ignored by firmware)
181 IN[1] - 0 = disable index file output
186 #define CX18_CPU_SET_INDEXTABLE (CPU_CMD_MASK_CAPTURE | 0x0010)
189 IN[0] - task handle. Handle of the task to start
192 #define CX18_CPU_SET_AUDIO_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0011)
195 IN[0] - task handle. Handle of the task to start
199 bit0: 1:mute, 0: unmute
201 #define CX18_CPU_SET_VIDEO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0013)
204 IN[0] - task handle. Handle of the task to start
207 #define CX18_CPU_SET_AUDIO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0014)
210 IN[0] - task handle. Handle of the task to start
223 #define CX18_CPU_SET_MISC_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0015)
226 IN[0] - Task handle
228 bit[15:0]: field 1,
235 #define CX18_CPU_SET_RAW_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0016)
238 IN[0] - task handle. Handle of the task to start
242 #define CX18_CPU_SET_CAPTURE_LINE_NO (CPU_CMD_MASK_CAPTURE | 0x0017)
245 IN[0] - task handle. Handle of the task to start
248 #define CX18_CPU_SET_COPYRIGHT (CPU_CMD_MASK_CAPTURE | 0x0018)
251 IN[0] - task handle. Handle of the task to start
254 #define CX18_CPU_SET_AUDIO_PID (CPU_CMD_MASK_CAPTURE | 0x0019)
257 IN[0] - task handle. Handle of the task to start
260 #define CX18_CPU_SET_VIDEO_PID (CPU_CMD_MASK_CAPTURE | 0x001A)
263 IN[0] - task handle. Handle of the task to start
266 #define CX18_CPU_SET_VER_CROP_LINE (CPU_CMD_MASK_CAPTURE | 0x001B)
269 IN[0] - task handle. Handle of the task to start
273 #define CX18_CPU_SET_GOP_STRUCTURE (CPU_CMD_MASK_CAPTURE | 0x001C)
276 IN[0] - task handle. Handle of the task to start
279 #define CX18_CPU_SET_SCENE_CHANGE_DETECTION (CPU_CMD_MASK_CAPTURE | 0x001D)
282 IN[0] - task handle. Handle of the task to start
285 #define CX18_CPU_SET_ASPECT_RATIO (CPU_CMD_MASK_CAPTURE | 0x001E)
288 IN[0] - task handle. Handle of the task to start
291 #define CX18_CPU_SET_SKIP_INPUT_FRAME (CPU_CMD_MASK_CAPTURE | 0x001F)
295 IN[0] - Task handle
296 IN[1] - output type, 0 - CC, 1 - Moji, 2 - Teletext
298 bit[15:0] start line number
302 bit 0: output user data, 1 - enable
304 bit 2: mux option, 0 - in GOP, 1 - in picture
305 bit[7:0] private stream ID
308 #define CX18_CPU_SET_SLICED_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0020)
311 IN[0] - type of data (0 for user)
315 #define CX18_CPU_SET_USERDATA_PLACE_HOLDER (CPU_CMD_MASK_CAPTURE | 0x0021)
319 In[0] Task Handle
321 Out[0] Reserved
323 Out[2] Video PTS bit[ 1:0] of last output video frame.
324 Out[3] Hardware Video PTS counter bit[31:0],
329 #define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022)
332 IN[0] - task handle
333 IN[1] - VFC enable flag, 1 - enable, 0 - disable
335 #define CX18_CPU_SET_VFC_PARAM (CPU_CMD_MASK_CAPTURE | 0x0023)
338 #define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000)
342 IN[0] - Physical offset where EPU has the local DDR mapped
344 #define CPU_CMD_DE_SetBase (CPU_CMD_MASK_DE | 0x0001)
348 IN[0] - Task handle. Handle of the task to start
354 #define CX18_CPU_DE_SET_MDL_ACK (CPU_CMD_MASK_DE | 0x0002)
357 IN[0] - Task handle. Handle of the task to start
363 #define CX18_CPU_DE_SET_MDL (CPU_CMD_MASK_DE | 0x0005)
367 IN[0] - Task handle. Handle of the task to start
369 #define CX18_CPU_DE_RELEASE_MDL (CPU_CMD_MASK_DE | 0x0006)
373 IN[0] - Task handle. Handle of the task
377 /* #define CX18_CPU_DE_RELEASE_BUFFER (CPU_CMD_MASK_DE | 0x0007) */
380 #define CNXT_OK 0x000000
383 #define CXERR_UNK_CMD 0x000001
386 #define CXERR_INVALID_PARAM1 0x000002
389 #define CXERR_INVALID_PARAM2 0x000003
392 #define CXERR_DEV_NOT_FOUND 0x000004
395 #define CXERR_NOTSUPPORTED 0x000005
398 #define CXERR_BADPTR 0x000006
401 #define CXERR_NOMEM 0x000007
404 #define CXERR_LINK 0x000008
407 #define CXERR_BUSY 0x000009
410 #define CXERR_NOT_OPEN 0x00000A
413 #define CXERR_OUTOFRANGE 0x00000B
416 #define CXERR_OVERFLOW 0x00000C
419 #define CXERR_BADVER 0x00000D
422 #define CXERR_TIMEOUT 0x00000E
425 #define CXERR_ABORT 0x00000F
428 #define CXERR_I2CDEV_NOTFOUND 0x000010
431 #define CXERR_I2CDEV_XFERERR 0x000011
434 #define CXERR_CHANNELNOTREADY 0x000012
437 #define CXERR_PPU_MB_CORRUPT 0x000013
440 #define CXERR_CPU_MB_CORRUPT 0x000014
443 #define CXERR_APU_MB_CORRUPT 0x000015
446 #define CXERR_FILE_OPEN_READ 0x000016
449 #define CXERR_FILE_OPEN_WRITE 0x000017
452 #define CXERR_I2C_BADSECTION 0x000018
455 #define CXERR_I2CDEV_DATALOW 0x000019
458 #define CXERR_I2CDEV_CLOCKLOW 0x00001A
461 #define CXERR_NO_HW_I2C_INTR 0x00001B
464 #define CXERR_RPU_NOT_READY 0x00001C
467 #define CXERR_RPU_NO_ACK 0x00001D
470 #define CXERR_NODATA_AGAIN 0x00001E
473 #define CXERR_STOPPING_STATUS 0x00001F
476 #define CXERR_DEVPOWER_OFF 0x000020