Lines Matching +full:0 +full:x03000000
13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
40 /* Read and auto increment until at address 0x0000 */ in cx18_av_verifyfw()
41 while (dl_control & 0x3fff) in cx18_av_verifyfw()
46 for (addr = 0; addr < size; addr++) { in cx18_av_verifyfw()
47 dl_control &= 0xffff3fff; /* ignore top 2 bits of address */ in cx18_av_verifyfw()
48 expected = 0x0f000000 | ((u32)data[addr] << 16) | addr; in cx18_av_verifyfw()
57 if (ret == 0) in cx18_av_verifyfw()
71 int retries1 = 0; in cx18_av_loadfw()
73 if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) { in cx18_av_loadfw()
81 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000, in cx18_av_loadfw()
82 0x00008430, 0xffffffff); /* cx25843 */ in cx18_av_loadfw()
83 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff); in cx18_av_loadfw()
86 cx18_av_write4_expect(cx, 0x8100, 0x00010000, in cx18_av_loadfw()
87 0x00008430, 0xffffffff); /* cx25843 */ in cx18_av_loadfw()
90 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000); in cx18_av_loadfw()
95 for (i = 0; i < size; i++) { in cx18_av_loadfw()
96 u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16); in cx18_av_loadfw()
97 u32 value = 0; in cx18_av_loadfw()
99 int unrec_err = 0; in cx18_av_loadfw()
101 for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES; in cx18_av_loadfw()
112 if ((value & 0x3F00) != (dl_control & 0x3F00)) { in cx18_av_loadfw()
131 0x03000000 | fw->size, 0x03000000, 0x13000000); in cx18_av_loadfw()
135 if (cx18_av_verifyfw(cx, fw) == 0) in cx18_av_loadfw()
137 0x13000000 | fw->size, 0x13000000, 0x13000000); in cx18_av_loadfw()
140 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000); in cx18_av_loadfw()
143 /* Audio output input 2 is 0 for slave operation input */ in cx18_av_loadfw()
144 /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ in cx18_av_loadfw()
145 /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge in cx18_av_loadfw()
147 cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0); in cx18_av_loadfw()
151 /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ in cx18_av_loadfw()
152 /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge in cx18_av_loadfw()
154 /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT in cx18_av_loadfw()
156 cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0); in cx18_av_loadfw()
158 /* set alt I2s master clock to /0x16 and enable alt divider i2s in cx18_av_loadfw()
160 cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687); in cx18_av_loadfw()
162 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6, in cx18_av_loadfw()
163 0x3F00FFFF); in cx18_av_loadfw()
164 /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */ in cx18_av_loadfw()
166 /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */ in cx18_av_loadfw()
167 /* Register 0x09CC is defined by the Merlin firmware, and doesn't in cx18_av_loadfw()
169 cx18_av_write4(cx, 0x09CC, 1); in cx18_av_loadfw()
173 if (v & 0x800) in cx18_av_loadfw()
174 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
175 0, 0x400); in cx18_av_loadfw()
184 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
191 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
196 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
201 v |= 0xFF; /* Auto by default */ in cx18_av_loadfw()
202 v |= 0x400; /* Stereo by default */ in cx18_av_loadfw()
203 v |= 0x14000000; in cx18_av_loadfw()
204 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF); in cx18_av_loadfw()
207 return 0; in cx18_av_loadfw()